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Separating Random and Systematic Defects

Laura Peters, Associate Editor -- Semiconductor International, 3/1/1999

Part 2 in this series of articles on Integrated Yield Management (see for complete articles), by Nick Atchison and Ron Ross of Texas Instruments (Santa Cruz, Calif.), demonstrates an improved method for determining the ratio of randomly dispersed defects to regionally-confined systematic defects that cause yield loss. It is one of several follow-on papers to 'A Comprehensive Sequential Yield Analysis Methodology,' in Semiconductor International, January 1999, p. 38.

The IYM model utilizes a non-causal pattern recognition algorithm to calculate yield limits Yd and Ys. The Integrated Yield Management triangle has a Limited Yield Analysis level that is divided into Yd and Ys levels, subdivided into Ydef7, Ypara7, Ydes and Ytest7, each of which are divided into yield limits for each type of defect, process parameter, etc. Accurate assessment of Yd and Ys depends on accurate estimation of Edge Zone Yield loss (outer 25% of wafer) and repeating defects or arrayed yield loss (Ya). The authors developed and tested automated programs for cluster analysis calculations, applied them to CMOS and BiCMOS products using multiprobe data from a significant number of wafers (>200) and found the Yd of the cluster analysis matched the Yd calculated from KLA defect monitor data to within 1%. Calculated yield limits were confirmed using computer simulations and engineering experiments, which agreed well with limits calculated by independent means.

The methodology, refinement of a method used by IBM (described in IEEE Transactions on Semiconductor Manufacturing, May 1995, p. 95), uses two types of data: multiprobe data with die yield and coordinate information and information that defines geometrically regular groups of dice that include 1 3 1, 1 3 2, 1 3 3, 2 3 2, 2 3 3 and 3 3 3 blocks of dice, called tiles. Yields of different tile sizes are calculated following the rule that all dice in a given tile must be good to produce a yielding tile. Using data in the center 3/4 of each wafer first, tile yields are plotted versus die size, and the data are then fit to the negative binomial equation:

Y= Ys
                         
(1 + AD ) a
a

Ys, D and a are varied to obtain the 'best fit,' and Yd is calculated once the defect density, D, is extracted.

Click for larger image.
Fig.1. When tile size equals reticle size, yield is zero for the curve with repeating defects, non-zero when defects are random only.

Array defects, such as those caused by a reticle defect, can be detected with large numbers of die per wafer, because the plot of yield versus tile size will show about the same yield for smaller tiles but will drop below the corresponding curve (for random defects only) as the tile size becomes larger (see Figure). Once yields of the tile sizes for all wafers are calculated and non-conforming data removed, average yield of each tile size for all wafers is calculated for the center portion of the wafer and passed to a two-step Gauss-Newton routine to fit the data to the negative binomial distribution (see paper for examples). Systematic test-related yield losses, often characterized as twinkling die (alternating pass/fail), can be corrected by assessing yield differences between testers, swap blocks, probe cards, etc.

The cluster analysis method allows for cross-checking of Yd and Ys from the limited yield analysis derived from parametric yield limit calculations and the defect yield limit derived from KLA defect monitor data. The method significantly helps prioritize yield improvement efforts.

Dr. Ron Ross, a fellow and manager of 'Advanced Yield Methods' at Texas Instruments' Storage Product Division (Santa Cruz), has held technical and managerial positions in product engineering, process and product development and yield enhancement. Ross holds a doctorate in Solid State Physics from Brigham Young University.
Nick Atchison is a process/product/device development engineer and an analytical programmer. His position is Principal Engineer at Texas Instruments, working in yield enhancement methods development. Atchison has an interdisciplinary bachelor's degree in Comparative Systems Theory from the University of California (Santa Cruz).

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