IBM Introduces New SOI Process

Peter Singer, Editor-in-Chief -- Semiconductor International, 9/1/1998

IBM (Hopewell Junction, N.Y.) once again announced a new manufacturing technology. Last year, it was among the first to announce it was putting copper into production. Last month, the company announced it had developed a "commercially viable" implementation of Silicon-on-Insulator (SOI) for mainstream applications.

IBM plans to incorporate SOI in its chip products beginning next year. IBM already produces SOI-based chips in a pilot production line in East Fishkill, N.Y., and will introduce the technology on its high-volume Burlington, Vt., manufacturing lines in the first half of 1999. SOI chips can require as little as one-third the power of today's microchips if performance levels are held constant. This is especially important for portable devices needing long battery life.

IBM plans to incorporate SOI technology into a wide range of semiconductors, including its merchant-market custom-chip products, standard products (such as the PowerPC microprocessor) and in chips used in its S/390, AS/400 and RS/6000 lines of servers.

Performance

IBM has built and tested SOI-based chips that have produced 20% to 25% cycle time and 25% to 35% improvement over equivalent bulk CMOS technology. This is equivalent to about two years of progress in bulk CMOS technology. According to Moore's Law, SOI causes a jump in the performance roadmap and compensates for some of the expected loss of bulk technology performance improvement in the next few years. The sources of increased SOI performance are elimination of area junction capacitance and elimination of "body effect" in bulk CMOS technology.

Low power

SOI has excellent capability as a low-power technology. Over the last few years, as people have been using more advanced technologies, one trend has been that the power of microprocessors has been going up. Increased power seriously limits the use of microprocessors, especially in mobile applications. IBM replaced bipolar transistors with MOS transistors due to the high consumption power of the bipolar transistors. Dropping the voltage is very effective in reducing chip power. The ability of SOI as a low-power source originates from the fact that SOI circuits can operate at low voltage with the same performance as a bulk technology at high voltage. As ASIC libraries for SOI are developed, SOI will have a tremendous impact on applications where low power is needed, such as portable and wireless applications.

Soft-error rate

One of the early benefits of SOI is the reduction in soft-error rate. Soft-error rate refers to upset of data in the memory by cosmic rays and background radioactive material. In fact, one of the first early applications of SOI has been in memories for space application, because the memories built on SOI were perceived to be more resistant to soft-error rate. As chips get smaller and the voltages drop, soft-error rate slowly becomes a major concern in server and mainframe chips. IBM's early studies indicate d that as CMOS is scaled into 0.18 µm range and voltages drop, SOI indeed has much lower soft-error rate than bulk CMOS.