Sampling Strategies for Sub-100 nm Overlay

Ruth DeJule, Associate Editor -- Semiconductor International, 9/1/1998

A t 0.18 µm design rules, the overlay budget (the relative displacement between a patterned layer and the previously defined layer) is expected to be 50 nm. Traditional approaches to improving the accuracy of overlay rely upon better equipment, including stepper stages and reticles, as well as improved stepper matching. In addition to these important factors, the choice of sampling plan can affect the estimate of overlay and the accuracy of the overlay correction dramatically. To address this issue, researchers at Advanced Micro Devices (AMD, Sunnyvale, Calif.), headed by Dr. Bharath Rangarajan, senior process development engineer, have studied various sampling strategies for sub-100 nm overlay.

Removal of correctable overlay errors often is achieved through adjustments to stepper parameters. The magnitude of these process corrections are determined typically by exposing test or pilot wafers and measuring the overlay at several points on the wafers. These measurements are fit to a model, and adjustments to stepper parameters are calculated. The amount of correction depends on the overlay error, the model used and the overlay-sampling plan.

The best representation of overlay is obtained by measuring the entire wafer. However, this would impact throughput negatively. In practice, a small number of points on a few wafers per lot is measured, and in many cases these parameters are determined by using the average from samples from several lots. Relying heavily on historical data, this method rules out the option of going back and completely mapping the wafer. The most common alternative implements a sampling plan.

Fig. 1. This sampling plan produces results close to that of full wafer sampling.

The researchers looked at nine different sampling plans that measure 25 points on a wafer. An SVG Lithography Micrascan II was used in the experiment. Comparisons were made to full wafer measurements. The researchers used two quantitative metrics to assess the different sampling plans. In the first method, equal weight was assigned to each of the correctable terms, which included X/Y translation, and field and grid distortion terms (magnification, rotation, skew). The statistical similarity in model parameters between the sample and a full wafer measurement was compared using P-values. The second analysis method minimized the amount of uncorrected (but correctable) error obtained from a sample when compared to a completely measured wafer.

The data shows that the sampling pattern can have a significant effect on the values of the various correctable parameters. A comparison of worst-case deviation between the various plans and a full wafer measurement is shown in Table 1. For a step-and-scan system, both analysis methods produced comparable results and identified three plans as "reasonably close" to full wafer sampling (Fig. 1). The improved performance of these plans is attributed to the fact that these patterns measure a larger number of grid points than conventional sampling plans, Rangarajan said at SPIE's 23rd International Symposium on Microlithography in Santa Clara, Calif. Because of the difference in correctable parameters, the optimal sampling plan may differ, depending on whether a stepper or scanner is used.