Leaping into the Unknown with 0.18 µm

By the end of this year, the world will see the first prototypes processed in 0.18 µm technology. In Europe, the first introductions will be realized by Siemens, ST and Philips (Eindhoven, The Netherlands). Within a year after that, other major manufacturers will follow. The European Union has launched a number of activities to stimulate the microelectronics industry and to address the specific challenges of 0.18 µm production.

For example, the EU's Advanced CMOS for Europe (ACE) project aims to develop front-end and back-end process steps and modules for 0.18 µm CMOS. The timing is in line with the 1997 SIA roadmap and with the advanced European industrial road-maps. The project, launched in March 1997 and coordinated by the Inter-University Microelectronics Centre (IMEC, Leuven, Belgium), is the successor of the ADEQUAT+ project and relies partly on the feasibility results of that project. The project involves eight partners, four from industry (Siemens, ST, Philips and Mitel Semiconductors) and four R&D institutions (IMEC; GRESSI; TU Delft and Fraunhofer, Berlin, Germany). It has a global cost of $33 million.

Fig. 1. Cross-sectional TEM photograph of a 0.18 µm PMOS transistor developed at IMEC. The device has an amorphous-silicon gate, a 4 nm thick gate oxide and Ti-capped CoSi2 silicidation.

Fig. 2. Cross-sectional TEM photograph of a 150 nm wide shallow trench with gate oxide and a polysilicon layer. The middle dark area corresponds to the silicon. The gate oxide does not show any thinning at the trench corners.

The goal of ACE is to possess the ability to process first complete 0.18 µm silicon this year. Major objectives of ACE are the development of patterning techniques (based on 248 nm deep UV lithography), fabrication of high-performance CMOS devices, development of multi-level metalization architectures of up to five to six levels of metal and the validation of these modules by industrial partners. Very aggressive specifications towards a high-performance and low-power 0.18 µm CMOS process were defined at the start of the project and are close to being met today. In addition, efforts are being undertaken to explore the scaling limits of 0.18 µm towards the 0.15 µm technology generation on patterning and front-end processing, which illustrate the dynamics of the project. The availability of state-of-the-art simulation tools in Europe has been of crucial importance in defining these specifications and in the optimization of the modules.

Last year, IMEC was involved in nearly 80 R&D contracts with the European Union. It participated in different MEDEA projects as well as in the ESPRIT/ACE project and the EU project on advanced CMOS in Europe, i.e. the development of 0.18 µm CMOS front-end and back-end technology.

The remainder of this article describes the challenges being faced by the industry in a number of key areas. These are being addressed in Europe by IMEC and others, but the same challenges are faced by semiconductor manufacturers worldwide.

Process challenges

While 0.25 µm technology is being introduced in pro-uction this year, the transition to 0.18 µm is being prepared already. This transition is said to be possibly the fastest technology change in the history of the industry. At the same time, it introduces a large number of significant challenges to be met. According to the 1997 SIA Roadmap, the introduction of new technologies has been accelerated by leading semiconductor companies from the traditional three-year cycle towards an approximate two-year cycle. The introduction of the 180 nm technology generation into the marketplace is forecast to occur next year instead of the previously predicted 2001. This acceleration deeply affects the way integrated circuits will be designed and manufactured in the coming years.

At this time, the different technology choices for 180 nm front-end processing have been narrowed, and solutions have been chosen. New back-end technologies will likely be introduced in different stages. First, 0.18 µm processing will be based on standard metalization techniques using Al alloys and SiO₂. In a next step, dual damascene will be introduced, especially when copper takes over from aluminum as the main on-chip conductor.

Of course, with each new technology generation, all aspects of IC processing must be developed and prepared for manufacturing in a production environment. The transition to 0.18 µm is no different in this sense. Developing devices in 0.18 µm technology operating at 1.8 V faces increasing challenges in device performance and reliability issues. These challenges are typical for each new technology generation and become more stringent with each device shrink (e.g. shallow junctions and gate-oxide thickness scaling) sucn as shown in figures 1 and 2. However, developing 0.18 µm technology pushes several process steps to their (physical) limits. To overcome these limitations, several critical challenges need to be handled, and a number of new technology steps will have to be introduced in 180 nm fab lines.

Deep UV patterning

Perhaps one of the greatest challenges can be found in the area of optical lithography associated with the use of deep UV lithography tools. Similar to the transition from 0.35 µm to 0.25 µm, in which i-line lithography was pushed to its limits, 248 nm deep UV will be extended as much as possible using different resolution enhancement techniques where needed. This poses enormous chal-lenges to all aspects of lithography for 180 nm technology. from mask making to metrology. The drive for higher NA, the subsequent reduc-tion in depth of focus (DOF), the use of resolution enhance-ment techniques and the stringent CD and linewidth re-quirements are push-ing lithography tool manufacturers to-ward greater opti-mization of their large-field high-throughput imaging systems. Process margins such as CD control within the same die are becoming increasingly narrow (Fig. 3). With the reduction in feature size and the use of enhancement techniques, mask-related errors have a greater impact on yield.

Fig. 3. Tilted view SEM of a 0.16 µm gate length shift register. Excellent line width control over topology can be achieved.

Focused ion beam (FIB) technology is being used increasingly by the photomask industry for reticle repair. But the greatest challenge in the area of patterning is the still-limited know-how on deep-UV patterning in a production environment. At the same time, steppers and reticles for 0.18 µm processes are very costly and require large investments. Although originally expected to be introduced for 0.18 µm, deep UV at wavelengths of 193 nm will have to be introduced for sub-0.15 µm processes.

Shallow trench isolation

Scaling down of feature sizes will also necessitate other isolation techniques. The localized oxidation isolation method (LOCOS) is still the most dominant isolation process used in silicon processing. However, continued device shrinks pose serious limitations on LOCOS-based methods in the deep submicron regime. The first limitation is the occurrence of the bird's beak. Scaling of the bird's beak often leads to excessive stress levels in the silicon, leading to defects. The other major limitation is the field oxide thinning effect. Several alternatives have been pursued, such as poly-buffered LOCOS (PBLOCOS), which can be used in 0.35 µm processes. Below 0.35 µm, PBLOCOS is not able to fulfill all the requirements, and other development directions had to be studied.

Polysilicon encapsulated LOCOS is a lateral isolation technique appropriate for a 0.25 µm CMOS process and can also fit the requirements for a 0.18 µm technology. For sub-0.25 µm technology generations, new approaches are necessary to ensure isolation with reduced flat topologies.

Perhaps the most promising technique is shallow trench isolation (STI). In this technique, 0.3-0.4 µm deep trenches are anisotropically etched in the silicon substrate by dry etching. Next, an oxide is deposited, and chemical mechanical polishing (CMP) is used to remove the oxide in the transition areas. This technique has the advantages of having no bird's beak and no encroachment. It also provides a better electrical isolation and allows for smaller dimensions. STI is a rather complicated process however, with many process steps, and serious efforts have been undertaken to simplify it as much as possible, such as the use of active area dummy structures. This has disadvantages in mixed analog/digital processes due to the increased noise and capacitive coupling between metal and substrate induced by these dummy structures.

At IMEC, a special process sequence was developed for STI to avoid the use of dummy structures. A nitride layer was added to protect the large field regions and to ensure that isolated small geometry active areas were not removed during oxide CMP. "As it is a complicated and costly process, it is now being introduced in the most advanced technologies," said Ludo Deferm, head of CMOS process integration at IMEC. "Still different companies are considering LOCOS-based processes for 0.25 µm CMOS. The majority will switch to STI for 0.18 µm and below."

CoSi₂ silicidation

While some manufacturers already have changed the silicidation module from TiSi₂ to CoSi₂ in 0.25 µm processing, CoSi₂ will be the standard silicidation for 0.18 µm and below. Silicidation with cobalt is well understood by now, and several solutions have been given to integrate it successfully into sub-0.25 µm technologies. Although it becomes very difficult to scale TiSi₂ below 0.35 µm, some reluctance to leave this material is apparent. Much has to do with the introduction of a new technology and its related integration issues such as stress and junction behavior aspects.

Copper and low-k dielectrics

Probably the largest potential technology gaps can be found in the multilevel metalization module. With the transition from Al alloys to copper as conductor metal, new materials and architectures are introduced into IC manufacturing and will require fundamental changes in process technologies. Therefore, first production of 0.18 µm chips will be based on "classical" metalization using Al/Cu alloys with more or less standard dielectric films. In a next step, damascene processes will be introduced in fab lines because of their many inherent advantages. Then new low-k dielectric materials can be implemented together with new metals like copper.

Although the 30% lower resistance compared to aluminum, superior electromigration properties and relatively low thermal budget make copper the eventual metal of choice, the industry still is not shifting to copper because of its natural reluctance to bring copper into manufacturing. This is due to the complexity of copper in damascene processes and the fear of contamination by copper in other processing steps. In fact, many IC manufacturers will take special precautions not to generate Cu contamination in the silicon. In addition, copper diffuses very easily, and diffusion barrier layers have to be incorporated.

Dual damascene integrates the plug and interconnection deposition into a single step, leading to a process that requires roughly 20% fewer process steps. Cu deposition will be done in two steps. A Cu seed layer will be deposited by PVD or CVD on top of the diffusion barrier (tantalum nitride, tungsten nitride, titanium nitride). The bulk of copper then can be deposited by electroplating or CVD. After via and trench fill, the Cu layer is planarized with CMP.

A large number of challenges remain to be met concerning Cu CMP. Apart from the material properties of copper itself, new barrier materials have to be developed that fit the requirements for polishing of these materials and copper. Commercial slurries are not yet readily available. Other problems include the easy erosion of densely packed small features, dishing of metal surfaces in large features and the fact that copper is a relatively soft metal, which makes it subject to scratches and embedded particles.

To find an appropriate dielectric material that answers to all criteria: low permitivity, high breakdown field, low leakage, no moisture absorption, thermal stability, good adhesion properties and a low defect density, among others is difficult.

Eventually, the combination of copper and low-k dielectric materials will be the solution for sub-0.25 µm processing and will allow the production of highly-reliable, high-speed, low-power chips at reduced manufacturing costs.

Yield management

The requirements for new systems-on-chip designs increasingly can be met with the 0.18 µm technology compared to earlier generations. This implies enormous challenges to yield management on all aspects of processing, from active area to interconnections. At the same time, it will require a transition to 200 mm and 300 mm wafer processing to keep manufacturing costs of large-die wafers as low as possible. With the further downscaling of feature sizes, small-sized defects start to play a critical role as they become comparable in size to metal line spacings for example, and their number increases exponentially. Thorough studies on classification and remedying of all possible defects become a very important issue. Finally, early introduction of new technologies in fab lines has to be undertaken with some precaution.

Although early time-to-market can imply risking a full drawback of a new processing technology, it will ensure a large market share and high profits when introduced in the right window of opportunity. At the same time, when full 0.18 µm industrial processes are finalized, 0.15 µm, a downscaled 0.18 µm process, and 0.13 µm are being prepared. First production using 0.15 µm processes will be ready early in the year 2000.

The transition towards 300 mm wafer processing has been slowed considerably but likely will occur starting from the end of this year.