Challenges for 300 mm Polished Wafer Manufacturers

The primary driver behind the desire to use 300 mm wafers is cost. Downward trends in semiconductor components prices have been a characteristic of the electronics industry since it began in the late 1950s. Today many sectors of that industry are under severe pressure to reduce prices. This presents key challenges to technologists looking for lower cost methods of manufacturing. Silicon wafer manufacturers are no exception to this type of pressure, and as they move into the 300 mm era, they are searching for new technologies that can sustain the low-cost, high-quality outputs required to meet customer needs.¹ Recent breakthroughs in silicon crystal growth technology have removed the uncertainty of crystal quality, and "perfect silicon" is a reality.² Understanding and controlling point defect reactions during crystal growth and cooling allows effective defect levels to be brought down to zero. The task of engineers and scientists working on wafering is to turn the single crystal into wafers using the simplest, lowest cost process, while meeting the stringent quality requirements of device manufacturers.

300 mm wafer requirements

Typical requirements for 0.18 µm geometry, 300 mm wafers are shown in Table 1 for various grades of wafers. As the product matures, only Grade 1 and a small number of monitor wafers will be required. However, during development and ramp up, lithography and furnace monitor samples are used to monitor process-induced changes throughout the fabrication process for qualification of photo-lithography tools and engineering tests. Test and particle monitor grades are used for tool qualifications and measuring particles added by various tools and processes, especially those associated with thin film depositions.

Future specifications will be tighter and may include front surface microroughness requirements at the 0.1 nm level, which will present additional challenges in final polishing and cleaning.

The basic technologies required to meet these specifications are available today, although some issues remain to be solved. The majority of issues revolve around achieving high throughput, yield, automation and handling.

Shaping

Wire saws now are established fully as the preferred method of slicing large diameter ingots. They have the potential to yield more slices per inch of crystal than conventional ID saws due to the thinner kerf losses associated with using a slurry-coated wire instead of a diamond-coated blade. Future dev-elopments center on the ability to mount multiple ingots per run and minimize kerf loss by going to smaller diameter wire.

Fig. 1. This shows the depth of damage dependency on grinding grit size.3

Current technologies create crystallographic damage to a depth of at least several tens of microns and produce some degree of bow and warp. It is necessary to remove these features to produce a flat, damage-free wafer. Traditional techniques include lapping and grinding, but these still leave some degree of crystallographic damage. Chemical etching techniques however, produce a damage-free product, but it is very difficult to meet the required flatness specifications. A key challenge is to find a process that can remove the damage quickly and efficiently yet still produce a very flat prime wafer. Typically, this has been achieved through a series of operations involving all of the above methods.

The typical depth of damage created in a given machining operation is equal to about 0.5X the average grit size for fixed grit applications such as grinding, as shown in figure 1. A similar situation occurs for loose grit applications such as lapping, where the damage depth is about 1-1.2X the grit size. The finer the abrasive, the slower the process; therefore a series of operations is used to improve overall throughput while removing the damage with successively gentler steps. Lapped or ground wafers are typically very flat, and subsequent steps used to remove damage should not degrade flatness. Lapping, a multiple wafer process, tends to be relatively labor intensive, while grinding, a single-wafer process, can be automated easily.

Grinding technologies vary considerably, with the ability to employ a wide range of grit sizes and to grind both sides of the wafer simultaneously if necessary. Developments focus on developing finer grit wheels that will not clog quickly and wafer chucks that will retain their shape over many operations in order to produce consistent shapes. Table 2 shows some general properties of wafer manufacturing processes.

Polishing

Historically, photolithography has been the driver for flatness improvement. The advent of more complex device structures has led to the introduction of chemical mechanical planarization (CMP) in which the front surface of the patterned wafer must be made flat to within tenths of a micron or better. This in turn, places stringent requirements on the starting wafer flatness. Therefore in many cases, CMP requirements are becoming the driver for wafer flatness. CMP typically is achieved with a high mechanical component from abrasive slurries, a hard pad and low removal rate. Conversely, chemical mechanical polishing in the wafer industry requires a higher chemical component to achieve the required damage removal rate and low mechanical action to avoid scratches.

In practice, multistage polishing is usually required, starting with one or more rough stock removal steps and ending with a finish polish step with very little removal. As the 0.18 µm generation approaches, 300 mm and some 200 mm products are required to be double-side polished (DSP) in order to achieve the required flatness levels. This presents interesting challenges in terms of handling and process design to avoid scuffs and scratches. On polished back surfaces, scuffs, scratches and handling marks are more visible, enhancing the need for automation. Automation of double-side polishers is a major challenge for the industry both in terms of technical solutions and cost of ownership. Technical challenges remain in relation to consistency of supply of slurries and pads for polishing. Pad-to-pad and lot-to-lot variations still generate variabilities in the results of polishing processes and will need to be resolved to meet the cost constraints of wafer manufacturers.

Newer technologies involving plasma etching, while not yet fully established as manufacturing tools in wafer manufacturing, show great promise. A plasma envelope created in SF₆ gas can be contained very precisely and will etch the silicon surface it contacts. The longer the plasma is held over an area of the surface, the more silicon is etched away. Precision wafer shaping (PWS) systems from Plasmasil (a joint venture between Integrated Measurement Systems Inc., IPEC, Phoenix, Ariz., and MEMC) can produce wafers with unsurpassed flatness. First, a wafer is measured for flatness. During the PWS process only the high spots are removed.

Another type of plasma tool involves etching the entire wafer in a plasma torch. Wafers are mounted on a carousel that rotates in the torch. A similar tool is also available from Tru-Si Technologies (Sunnyvale, Calif.) under the acronym ADP (Atmospheric Downstream Plasma). These methods are somewhat faster but have not yet demonstrated the precision of PWS.

Cleaning

Cleaning specifications have developed considerably in the last few years to the extent that now it is necessary to produce wafers that are free from particles that generally are not visible until after a CVD nitride or similar deposition step in the customer's device line. This has been an interesting challenge for process, equipment and metrology groups alike. Success has been achieved through a detailed understanding of the fundamental chemistry, fluid dynamics and particle kinetics involved in cleaning. Single- and multiple-cleaning tank systems have been demonstrated successfully. Both types are suited to wafer manufacturing at various points in the production line and, if applied correctly, are capable of meeting current generation specifications. A key part of meeting the specifications is reliability and consistency of results from cleaning tools. Shive et. al.⁴ have demonstrated that excellent metal levels can be sustained through in-line mon-itoring of cleaning solutions with ICP-MS every few minutes. Existing capabilities allow detection of impurities in chemical baths down to better than parts per trillion levels. This has enabled true process control, as opposed to product monitoring, and allows immediate identification and correction of deviations from specified limits. Current technologies with innovations such as this can meet most specification requirements of the next two generations of wafers. Challenges revolve around using recycling and regeneration methods to achieve lower chemical and water consumption.

Metrology

Relatively few 300 mm metrology tools are available today beyond beta test versions. Wafer handling and metrology capabilities are not developed fully to production-worthy performance levels, and current market conditions have caused equipment manufacturers to delay their 300 mm programs along with the rest of the industry. Supplier companies are being challenged in terms of sensitivity, reproducibility and reliability of equipment.⁵ Some systems have demonstrated a good overall capability in this respect but will be required to continue extending their capabilities in order to keep up with the need to detect smaller and smaller defects. Two key areas of concern for metrology tool developers are the requirements for lower edge exclusion areas and backside handling. Some device manufacturers are insisting on lower edge exclusion areas on wafers. This is reflected in the NTRS roadmap.⁶ This adds issues of measurement close to the wafer edge and handling of wafers with very narrow exclusion areas, both adding to the cost of metrology tools. The industry appears to be struggling with a lack of data to support the cost benefits of 100% edge handling tools. The development cost of such tools will be quite high and require significant lead times.

Packaging

The use of Automated Material Handling Systems and minienvironments in 300 mm fab lines is now established as a preferred philosophy. Cooperation between suppliers is leading to established standards for Front Opening Unified Pods (FOUPs). Current FOUP designs are not suitable for wafer shipping between factories, so new shippers are being developed. Reuse of packaging materials is an advantage in terms of ecology and cost, and this requirement is leading to new materials and concepts for delivering and transporting wafers. The logistics of reuse are still to be worked out, but one solution might be for device lines to transfer wafers to their own FOUPs on arrival in the line and for the shipper to be returned to the wafer vendor, together with all the secondary packaging material. In this way the wafer vendor can be sure that a process in the device line has not contaminated the shipper.

Twenty-five-wafer, Front Opening Shipping Boxes (FOSBs) are based on the pod design concept and are quite different from traditional wafer shippers. Empak, Fluoroware (Chaska, Minn.) and Shin Etsu Polymer (SEP) are currently the major players, with Asyst and Kakizaki (Tokyo, Japan) also developing solutions. The industry has little experience shipping wafers in pods. Challenges ahead include ergonomics, automation, cleaning, drying reusability and cost of ownership. The secondary packaging also should be reusable and capable of high packing densities. Suitable designs are already in use for 200 mm wafers.

Conclusions

The key challenges for 300 mm wafer manufacturers involve finding combinations of tools and technologies that can meet the stringent requirements of device manufacturers (Table 3). High on the list of requirements is the price and cost of silicon wafers. Understanding this at the design stage of 300 mm wafer manufacturing lines means that factories can be optimized to find the simplest, most cost-effective technologies, factory layouts and support systems to meet demands. Most of the requirements for 0.18 µm generation wafers can be met today with available technologies. Future generations will be pressing flatness ability, microroughness, metrology limits and consistency of process supplies such as slurries and pads. Ecology and economics will drive the effort to use recycling of many consumables including slurry, chemicals, deionized water and packaging materials. It is essential that the entire supply chain can meet this challenge.

The role of cooperative consortia such as I300I and SEMATECH will assist in fostering joint development projects on non-competitive research and new industry standards. Cost-of-ownership models are now a routine part of deciding which tools and processes to install. Only those meeting this challenge will be successful.

Acknowledgments

The author wishes to thank members of the MEMC wafering technology department, particularly Henry Erk, Z.J. Pei, Dale Witte, Dong Hou and Larry Shive for many helpful and interesting discussions.

References

1. S. Brunkhorst and D. Sloat, Solid State Technology, Vol. 41, No. 1, 1998, p. 87.
2. MEMC Public Announcement, Wall Street Journal, April 13, 1998.
3. Z.J. Pei (Private Communication).
4. Larry W. Shive, Philip Schmidt and Kenny Ruth, "In-line Monitoring of Metal Contamination in Cleaning Baths by ICP-MS," to be published in 1998.
5. H.R. Huff and R.K. Goodal, "Silicon Materials and Metrology: Critical Concepts for Optimal IC Performance in the Gigabit Era," Diffusion and Defect Data, Part B (Solid State Phenomena) 47-48, p. 65.
6. Semiconductor Industry Association , National Technology Roadmap for Semiconductors, 1997.

Graham R. Fisher is director of wafering technology at MEMC, managing the development of new technologies for producing silicon wafers. He joined MEMC in 1985 as a senior research specialist and moved up through the ranks to become technical operations manager in the Advanced Product Division in 1993 and in 1994 became director of manufacturing technology for U.S. operations. Graham has a bachelor's degree in physics from the University of Salford in England and a doctorate in materials science from the University of London.