Semicon West '98 Wrap-up

John Baliga, Associate Editor -- Semiconductor International, 9/1/1998

T he San Jose portion of Semicon West '98 featured interesting product and technology introductions for packaging applications. Of course, die bonders and wire bonders have continued to increase their speeds and decrease their minimum pitches. In addition to new materials and tools, new packaging and productivity concepts also emerged.

Ablestik Laboratories (Rancho Dominguez, Calif.) introduced its Thermaxx line of die bond adhesives starting with the Thermaxx 2600K. The "polymer" material contains up to 90% metalic content. The concept is to provide something like eutectic solder, but with the handling and dispensing advantages of a polymer material. The company claims a thermal conductivity of 20 W/mK for the material, much higher than typical polymer materials.

Johnson Matthey Electronics (JME) announced several organizational changes. Company headquarters has moved to Eden Prairie, Minn., and Advanced Circuits, a JME company since 1995, changed its name to Johnson Matthey Advanced Circuits Inc. (Minneapolis, Minn.). JME also signed a joint marketing agreement with Flomerics (Marlborough, Mass.) to provide a combination of design software, validation services and components to speed the thermal management aspect of package development.

Inspectec (Carmiel, Israel) showed its kerf inspection system for inspecting diced wafers. The system uses automated visual inspection and analysis to differentiate chipping from test structures and silicon dust consistently. The machine is designed to give fewer false rejects, as well as provide statistical process control (SPC) for the wafer saw process. The company has tools installed at the Siemens facility in Regensburg, Germany, and at a Motorola facility in Phoenix, Ariz.

Electroglas (Santa Clara, Calif.) introduced its QuickSilver series inspection systems for 100% visual inspection of devices, mostly at the wafer level. Systems in the series are designed for inspection of microstructures, wafers and solder bumps.

Cognex (Natick, Mass.) introduced its PatInspect vision software technology. Based on the company's PatMax object location technology, PatInspect is designed to "understand" what is missing or added to an image, regardless of rotations or changes in scale. The company believes this method is more robust than correlation technologies in a real manufacturing environment. Also, Cognex recently acquired vision technologies from Rockwell Automation's (Mayfield Heights, Ohio) Allen-Bradley machine vision business.

Daymarc (Littleton, Mass.) showed its Enterprise test handling system for test-in-tray processing. The system accepts and tests devices in JEDEC trays, eliminating the need for changeover kits. Trays are plunged up to the contactors, and test data is kept in tray map files for off-line binning.

New ideas for 3D packaging were presented at the show. Well-known methods exist for stacking memory chips, but they are mostly for saving space. Talk is starting about stacking other devices to speed communication between them. Tru-Si (Sunnyvale, Calif.) presented the idea of thinning indiviual dice to a 25 µm thickness for the purpose of stacking them in a small space. Ball Semiconductor (Allen, Texas) presented the concept of connecting silicon spheres with solder balls in a three-dimensional arrangement. These concepts are an alternative to systems-on-a-chip (SOC) in that components of a system can be made separately to avoid process trade-offs.

The packaging concept Ball Semiconductor plans to use is similar to that in newer chip scale "packages." The finished ball is coated with a polymer material that is color-coded for the ball's function. In the concept, a ball would not be a device, but a device component, like a register or an I/O array.

W.L.Gore Associates (Eau Claire, Wis.) introduced its Via on Chip Pitch packages using its MICROLAM substrate material. The material is made from expanded PTFE (ePTFE) that acts as a scaffolding for adhesives, reinforcing fillers or other desired performance enhancers. The substrate is designed to have the same coefficient of thermal expansion (CTE) as copper in all three directions to improve reliability. Gore's Via on Chip Pitch packaging process for flip chip devices has interconnect vias in the package on the same pitch as the die I/Os. This eliminates the need for fan-out, simplifying package design. The company claims via pitch capability down to 122 µm on its MICROLAM substrates.