Capturing the Essence of the World's First Copper Chips
Fig. 2. Unlike subtractive aluminum/tungsten interconnects, dual-damascene architecture enables zero offset between vias and connecting metal levels for lower overall resistance.
Staff -- Semiconductor International, 10/1/1998
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| Fig. 1. Device cross-section shows the topography of seven levels of fully-planarized metal. (All photos courtesy of ICE) | |
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| Fig. 2. Unlike subtractive aluminum/tungsten interconnects, dual-damascene architecture enables zero offset between vias and connecting metal levels for lower overall resistance. | |
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| Fig. 3. Three-dimensional illustration shows polysilicon gates, shallow trench isolation regions, tungsten local interconnects and copper metal 1 levels. (note: interlevel dielectric has been removed). | |
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| Fig. 4. Transistor-level detail of the 400 MHz microprocessor shows a 0.12 µm gate length. | |
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| Fig. 5. Three-dimensional illustration of poly gates and tungsten contacts with the first copper layer sheared off for illustration purposes. | |
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| Fig. 6. IBM claims the first commercially-viable use of SOI for mainstream applications. | |
The
industry's first copper-based chips are now a little less mysterious than a
year ago. Construction analysis courtesy of Integrated Circuit Engineering (ICE)
reveals manufacturing details of perhaps the most interesting chip on the planet
today, the Power PC750 microprocessor, the first production device with what
some call a "copper inside" process. SEM images (Figs. 1-5) provide insight
into the processes used to produce the device.
This incredible technology breakthrough to copper, completely replacing aluminum interconnects, is augmented skillfully with such features as 0.12 µm gate lengths, 0.55 µm metal pitch (minimum) and 6.35 million transistors on a 43 mm2 die. The local tungsten interconnect uses a damascene process, while five of the six layers of copper use dual-damascene architecture. Low resistance cobalt is used for silicided n+ and p+ polysilicon and source/drain diffusions. The overall process is comprised of an estimated 26 mask levels. Interestingly, the analysis showed no use of low permittivity (low-k) dielectrics or other spin-on films.
ICE also measured a variety of features including 0.30 µm copper interconnect width, 0.30 µm diameter tungsten contacts and 0.125 µm deep p and n junctions with 0.05 µm shallow extensions. Though the precise stoichiometry of the TaN layer is unknown, IBM did use TaN as a barrier metal for copper, with an estimated thickness of 30 nm. IBM's specifications for the Power PC750 include:
- n-channel Leff of 0.11 µm,
- Idsat n-channel of 600 µA/ µm,
- p-channel Leff of 0.24 µm and
- Idsat p-channel of 270 µA/ µm.
IBM's 0.22 µm CMOS 7S technology, qualified this year, is the first to use damascene-copper wiring. With copper linewidths ranging from 300 to 810 nm, the replacement of aluminum with copper substantially lowers BEOL resistance and capacitance. Aside from the 40% lower sheet resistance afforded by copper (accelerating device speed from 300 to 400 MHz for the same chip), in an article titled "Interconnection Scaling to 1 GHz and Beyond" (see www.chips.ibm.com/ micronews/vol4-no2/ interconnection.asp),IBM's Anthony Stamper highlighted other advantages of damascene-copper over subtractive aluminum processes. For instance, copper-damascene reportedly allows lower random and systematic defect density. Technology extendibility also is improved due to copper's lower resistivity and lower resistance and capacitance variability in the damascene structure.
Stamper further indicated improved metal line/via/line photolithography overlay with copper-damascene processes. In addition, a 2X increase in wire and via aspect ratios in high-performance CMOS (to 1.6:1 for wires and 2.0:1 for vias from 0.5 to 0.25 µm device generations) inevitably has resulted from needs to contain RC interconnect delay times. However, this reverse scaling increases defect density and manufacturing costs associated with standard subtractive-aluminum etch process. Because of copper's 40% lower sheet resistance, the aspect ratio required to achieve a given RC of the interconnect decreases by about 50% or 40% at a given aspect ratio. Via dimensions also can be scaled at the same rate as metal linewidths in a copper-damascene structure. The elimination of high-resistance tungsten reduces via resistance from 1.5 to 0.5 ohms per via for 450 nm vias in a 0.25 µm BEOL process. IBM's electromigration and stress-migration data indicate damascene copper wires exhibit more than two orders of magnitude improved reliability relative to subtractive aluminum wiring.
Copper interconnect technology is referred to loosely as "copper inside," with foundries already receiving requests for copper-based 0.18 µm processes. IBM is offering copper foundry services, with planned production of Power PC750 in mid-1999, when copper chips will make their appearance in personal computers.
As if analysis of the first copper-based chip in the world is not enough, ICE also provides a preview of an IBM chip using silicon-on-insulator (SOI) technology (Fig. 6), slated for commercial availability next year. This test device showed an insulating layer thickness of 0.4 µm. IBM plans to use SOI technology on its merchant market custom chips, standard products (such as Power PC chips) and its S/390, AS/400 and RS/6000 lines of server processors. Using SOI, a microprocessor designed to operate at 400 MHz can reach speeds over 500 MHz. SOI devices can require as little as one-third the power of traditional devices.
The Power PC750 analysis report is available from ICE for $1980. Free posters
of the PC750 are also available (see www.ice-corp.com).
ICE has provided analytical laboratory services and technical training for the
semiconductor industry for over 30 years, with headquarters in Scottsdale, Ariz.
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