Europe Moves Towards the 0.18µm Era
Staff -- Semiconductor International, 10/1/1998
Most
major European semiconductor manufacturing companies and many research organizations
are participating in the Esprit Adequat project. This is claimed to have led
the world in pioneering deep sub-micron CMOS processes since 1992. The early
Adequat1 and Adequat2 projects demonstrated 0.35 and 0.25 µm front-end
processes, but Adequat+ now has achieved 0.18 µm front-end CMOS processes
as well as 0.25 µm processes for the back-end final layers of chips.
The core goal of Adquat+ was to provide scalability and assess impact of smaller design rules onelectrical characteristics of devices. This move to 0.18 µm required addressing challenges at all stages of processing and especially to find process sequences with more latitude. It was necessary to investigate alternative solutions for dielectrics, junctions and conductors and develop new 0.18 µm device architectures and novel schemes to connect them.
Adequat+ has shown the feasibility of using 0.18 µm channel lengths in CMOS tranistors (Figs. 1 and 2). It also has demonstrated devices operating from supply voltages down to 1.8 V and low-voltage technologies for 0.25 µm transistors. Layout rules for 0.25 µm back-end processing using 0.4 µm lengths were obtained as well as a 0.5 µm space for contacts and 0.4 µm interconnects in the first metal layer. A stack of five metal layers using this process also was demonstrated.
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Fig. 1. This 0.18 µm structure was produced in Adequat+ work. (Source: IMEC) |
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| Fig. 2. This is an enlarged view of a 0.18 µm gate. (Source: IMEC) |
All Adequat+ partners are expected to introduce 0.18 µm device technology.
It will form up to 5% of their device portfolio by 2001 and then increase rapidly
in volume. The project is coordinated by IMEC, Leuven, Belgium. Project participants
include Siemens AG and Fraunhofer Gesellschaft (Germany), GEC Plessey Semiconductors
and the University of Warwick (UK), Philips Semiconductors and DIMES (the Netherlands),
SGS-Thomson Microelectronics (France/ Italy), Lamel and the Universities of
Bologna and Pisa (Italy), the National Microelectronics Research Centre (Ireland),
GRESSI and GCIS (France). 
