Making Room for More Performance with Chip Scale Packaging

John Baliga, Associate Editor -- Semiconductor International, 10/1/1998

There are ~50 different chip scale packages in existence today, falling into four general types: custom leadframe, flexible interposer, rigid substrate and wafer level package.³
Table 1 lists them according to general type.⁴

Applications

Currently, CSPs are limited to use in moderate I/O ICs. Flash memory has adopted chip scale packaging fastest, while other memory and logic ICs have been going into CSPs as well. The I/O limitation comes mainly from the reduced lead or ball pitch combined with limitations of board assembly. Current state-of-the-art lead pitch for board assembly is ~0.4 mm. While the state-of-the-art ball pitch for a flip chip in a package is below 0.25 mm, the best ball pitch on a board is still ~0.5 mm. Higher I/O ICs also tend to produce more heat, placing more demands on heat removal and relief of thermally induced stress. Providing compliance to mitigate coefficient of thermal expansion (CTE) differentiating between silicon and the board becomes more difficult.

Smart cards provide another application for CSPs. Though COB techniques are used typically, CSPs are becoming small enough for smart cards. Also, it is possible to package an IC that cannot be taken apart without destroying the chip. This adds security against reverse engineering of a lost or stolen card. This is one advantage that ShellCase (Jerusalem, Israel) claims for its packages.

Wafer level packaging

Three of the four general CSP types are miniature forms of more conventional packages. Wafer level packaging is different, because most, if not all, packaging is done before device singulation or wafer saw. In many cases, devices cannot be reworked, so they must be tested and burned in at the wafer level. Many companies are starting to perform burn-in at the wafer level, Motorola (Austin, Texas) being one of the most recent to announce a developed process.

Fig. 2. More chip scale packaging is happening at the wafer level, where singulation of devices is the last step. (Source: Flip Chip Technologies)

The Ultra CSP from Flip Chip Technologies (Phoenix, Ariz.) is essentially a flip chip that uses a two-step redistribution process with benzocyclobutene (BCB) as the dielectric (Fig. 2). BCB has low water absorption and is hydrophobic, making the layer function as a popcorn resistant package. The Super CSP from Fujitsu (San Jose, Calif.) also performs most packaging before saw. The encapsulant is pressed onto a bumped wafer, so that bumps are exposed.⁵ Solder balls are placed on bumps after the devices are singulated. Though the protective coating for these packages may not provide much compliance, both packages have promising reliability data without an underfill.

Tessera's (San Jose) tiles technology is an application of its µBGA packaging technology at the wafer level. From an electrical standpoint, the package is part of the device. In essence, the top two or three metalization layers from the chip are moved to the package. Mechanically, it is different from other wafer-level packages, because it has a compliant layer between the chip and package.

The ShellPack package by ShellCase sandwiches a thinned wafer between glass plates. The top glass plate is scribed to expose the I/O pads, and metal is patterned to make external contacts before the devices are singulated. The finished package is the same thickness as a bare die and is said to be more robust. The company recently released reliability data for the BGA version of its package, which is comparable to the peripherally leaded version.

An important aspect of chip/package yield, which has not been addressed historically for any kind of device, is the use of feedback from the packaging house in the wafer fab. If packaging is done at the wafer level, yield data at test can be used more easily in the fab, especially if packaging is done in the wafer fab. Also, in the case of the tiles concept, feedback is absolutely necessary, because the device is not electrically complete until packaging is done.

Chip scale interconnection

Packages that have been reduced to the size of a die must be able to perform functions with a certain efficiency. In a very small space they have to route I/Os, conduct heat, provide mechanical compliance and protect the die. A variety of innovations has begun to emerge in the area of interconnection to route the I/Os efficiently.

The number of electrical interconnections has increased on the chip with added metalization layers, in the package with added build-up layers and on the circuit board with added build-up layers and double-sided assembly. The chip, the package and the board have been separate entities historically. The chip always has been a complete electrical component needing a package only for mechanical and thermal reasons. The package always has been the interface between that complete electrical component and other circuits, and it was large enough to contain the chip. The board made connections between the devices and with the outside world. MCMs started to blend the board and the package as an efficient way to connect chips.

With CSPs, blending is starting to occur between the chip and package. In Tessera's "tiles" concept, the chip is no longer the finished device. The topmost interconnection layers on the chip that handle power, ground and some clock signals are moved out the package. In some cases, interconnections for those functions in the chip and in the package exist mainly for routing purposes and are redundant from an electrical point of view. Removing this redundancy reduces the number of interconnect layers that must be made on the chip, potentially reducing wafer fabrication costs.

In some cases, the package may be nothing more than a coating or another interconnect layer placed on the chip after wafer fab, as with Ultra CSP and Super CSP. What makes these devices eligible to be called packaged is that they can pass JEDEC reliability tests without use of an underfill or glob-top encapsulant. The choice of encapsulant material in each case is such that only a thin layer can provide necessary protection.

The 1997 National Technology Roadmap for Semiconductors⁶ addresses the concept of chip and package merging for radio frequency and mixed signal packaging. "Microwave packages are presently regarded as separate elements wrapped around the device/circuit after it is designed. Advances in BGA packages, fine pitch BGA/CSP packages and flip-chip interconnect will eliminate the package as a separate element." Though this may seem to have only limited relevance, it describes the current state of the art in computing. Data bus speeds are approaching 100 MHz, the edge of the microwave regime.

Another form of blending in the CSP arena is happening between the package and board. In many cases, the package substrate is a miniature circuit board containing one chip. This presents an opportunity to leverage existing PCB technology in CSPs.⁷

Multichip CSPs

Though CSPs exist as replacements for multichip modules, there is still a desire to package multiple chips as a unit. A number of companies are making stacked memory in CSPs, and Hightec MC AG (Lenzburg, Switzerland) is placing multiple chips on a flex substrate and folding it to stack the chips.⁸

These are examples of three-dimensional packaging, which is starting to present itself as a viable method. Technologies are starting to develop that will allow thinned dice to be stacked on each other, not only to conserve space, but also to put active devices closer in ways not possible on a two-dimensional surface.

Productivity and testing

CSPs have been adopted most widely in flash memory applications, because those applications were ready for the new package types. Adoption of CSPs in other areas like DRAM, SRAM and programmable logic is starting to take place. One cost barrier to wide adoption of CSPs is productivity at assembly and test. With assembly capabilities currently available, the largest productivity barrier is testing.

Wide adoption implies wide participation by all companies involved, including test and assembly houses, board assembly contractors, end product companies and their suppliers. The key to wide participation is having standards that remain in place long enough for a sufficient number of companies to benefit. With 50 or more different types of CSPs, I/O pitchs ranging from 1.5 mm to below 0.4 mm and die shrinks occuring every year or two, stable standards are difficult to find.

One way to streamline testing is to test before singulation. Sometimes, this means testing strips of devices, sometimes at the wafer level. Sorting then would be performed after singulation and devices discarded after packaging. This means packaging cost will have to be low and yield high. With the increase in wafer-level packaging, wafer-level testing is becoming more desirable.

Materials and technologies

CSPs have brought new materials and technologies into the packaging realm. One is vacuum encapsulation, introduced by Tessera. The use of vacuum, in the form of "blurping," is not new for eliminating voids in an encapsulant. Vacuum encapsulation though, uses pressure and vacuum in the opposite order. The vacuum is applied to bonded devices first. The encapsulant is dispensed, and it creeps through the desired areas. Afterwards, devices are brought back up to atmospheric pressure in a controlled manner, closing any voids that may exist in the encapsulant. Both Asymtek (Carlsbad, Calif.) and Speedline Fluids Dispensing Systems (Haverhill, Mass.) have made equipment for this process.

Dow Corning has provided new encapsulant materials. Benzocyclobutene (BCB) is not a new material; it has been proposed as a dielectric material for multilevel metal structures on the chip. Its use as an encapsulant is new however, and it is being used on the Ultra CSP and on offerings from Pac Tech (Nauen, Germany). Dow Corning also developed specialty materials for Tessera's µBGA silicone-based encapsulants and the material for the "nubbins" spacer.

Future needs

Fig. 3. Standardization of ball pitches and sizes can allow more companies to participate in board assembly of CSPs. (Source: Tessera)

In addition to developments in materials and technologies, future implementation of chip scale packaging depends on improvements in circuit board technology. The I/O pitch on CSPs will scale down along with semiconductor feature sizes, and the decrease in the minimum feature size on semiconductors is happening faster than the decrease in PCB bond pitch.⁹

According to J-STD-012, a joint industry standard on flip-chip and chip scale technologies, substrate materials also need to develop further. Ceramic materials need improvement in surface roughness and interconnect adhesion if their use is to extend. Polymer materials must develop further. Epitaxial diamond films have been proposed for heat spreading in packages where an added heat slug or spreader is impractical.

Productivity also must increase in the packaging facility to keep costs down. Computer integrated manufacturing (CIM) techniques will have to be employed to a very high degree to keep production volumes up while staying agile enough to change with market demands. A number of packaging facilities currently are using the same CIM systems used in front-end fabs.

Possibly, standardization is most important. Standardizing on reasonable array pitches can increase the number of companies participating in the CSP arena, allowing the CSP market to flourish enough to meet market demands.¹⁰ Standardizing ball sizes and package heights can make assembly much easier also, allowing more companies to participate in board assembly of CSPs (Fig. 3).

References