Stepping Up to the Copper/Low-k Challenge
Some say the semiconductor industry has more combined knowledge and technical expertise than any other industry in the world.
Laura Peters, Senior Editor -- Semiconductor International, 5/1/1998
Semiconductor leaders are preparing to bring in copper and low-k based interconnects to replace traditional aluminum/SiO2 systems, which will require radical and fundamental changes in many different technologies. With every variable in the metalization process -- every structural change, every new etching and polishing process and the introduction of every new material -- comes the possible introduction of problems. Even relatively small changes in semiconductor processes of the past have resulted in challenges that were not foreseen during development stages and only became apparent when moved into the production line. The most recent example of this came with the use of low-k (3.5-3.6) fluorinated oxides, once viewed as a drop-in replacement for SiO2, until unforeseen problems delayed their use in fab lines. Like the industry's traditional "fishbone" diagrams used to trace the possible causes of yield problems, for instance, any number of factors in copper and low-k will influence the electrical characteristics of the final device.
Key challenges in the copper/low-k plan include not only the selection
and qualifications of a variety of new materials but also the
integration of these materials into the semiconductor structure. Device
manufacturers are creating and testing a variety of damascene and
dual-damascene structures, both of which defy traditional
deposition-and-etch methods of pattern creation that the industry has
been using for more than 40 years. This change could be compared to
early transitions from lift-off techniques to deposition and etch, wet
etch to dry etch or perhaps the switch from negative to positive
photoresists. None of these transitions was trivial, and none occurred at
0.18 µm geometries.
Demands on the low-k dielectric (<3.9) include the development of a robust, production-worthy film with cleaning, etching and polishing characteristics similar to those of thermal or TEOS-based deposited oxides.
Because via and contact etching precede metal deposition, a nitride layer is practical for etch stop. However, because of the high dielectric constant of silicon nitride (~7), this layer must be as thin as possible. A dielectric sidewall may also be needed to strengthen the dielectric and provide the proper barrier to the metal interconnect.
Once the vias are opened, subsequent metal deposition requires a suitable barrier layer, a glue layer for the copper, copper filling technique and CMP (stay tuned for next month's cover story on copper for more details). The integration issues associated with even single damascene structures are daunting, requiring unprecedented cooperation among device design, development and manufacturing teams. Dual damascene further challenges lithography, which is already pushed for 0.25 µm devices.
With all these challenges comes a myriad of opportunities for engineers. Solving issues of new material characterization, etching and polishing behavior, and interface engineering could not be more exciting. To be part of the transition from traditional aluminum interconnects to copper means playing a part in a revolution in terms of the way semiconductors are made. Most importantly, the teams of engineers that devise the most cost-effective means of fabricating devices using copper and low-k will become the heroes of high technology, hopefully accelerating their companies to more competitive positions in the marketplace with new levels of profitability.
Some say the semiconductor industry has more combined knowledge and technical expertise than any other industry in the world. Though this is a sweeping statement, in many ways I believe it is well supported. The more people I speak to, the more impressed I become with their technical savvy and ability to innovate. If there are a thousand potential problems associated with fabricated devices with copper and low-k materials, I would expect R&D and process engineers to be able to anticipate at least 800 of them before first silicon. The industry has the genius required to plan and execute the momentous change to copper and low-k. The question becomes, who will get there first?
