FIB Techniques to Debug Flip-Chip Integrated Circuits

		At a Glance
	Next-generation high-performance microprocessors will use flip-chip packaging technology. With this technology, conventional frontside probing and traditional blue wire circuit editing of the packaged chip is not practical. We have developed a new technique for directly accessing metal signals from the backside of the chip. We describe some basic features of flip-chip technology, followed by a description of the new probing and blue wire editing technologies.

Flip-chip packaging, also known as C4 (controlled-collapse chip connection), is a departure from the conventional wirebond packaging that has been used to date to package integrated circuits (ICs). With C4 packaging, a direct electrical connection is achieved between the chip and package through solder bumps that connect bonding pads on the chip to corresponding pads on the package (Fig. 1). Unlike wirebond technology, which only allows peripheral bonding, C4 bumps can be placed anywhere on the die. This leads to a very low inductance power distribution to the chip, which is one of the major advantages of C4.

With this arrangement, there is no longer any access to circuitry for conventional physical probing while the chip is packaged. C4 packaging therefore mandates development of novel techniques for probing and circuit editing during silicon debugging.

Testability of internal nodes

Enhanced testability features, such as the implementation of SCAN latches, provides increased observability and controllability of internal logic and can be used for much of silicon debugging and failure analysis. However, techniques such as SCAN are only able to provide logic states on a given node and do not necessarily provide visibility into the physical fault location between SCAN latches. Furthermore, this technique cannot be used to measure critical analog parameters such as voltage levels, signal rise and fall times, and transient noise spikes. In order to make these types of measurements, it is necessary to use some type of physical probing technique such as an electron beam (e-beam) or a blue wire circuit edit.

The requirement to physically probe the chip for electrical waveforms arises when analyzing problems caused by circuit sensitivities. ¹ Examples of these types of problems include the following: capacitive coupling between interconnect lines; on-chip inductance; sense amplifier analysis; circuits with feedback loops; phase lock loop problems; self-timed circuits; oscillations; and non-scanned circuits.

Design verification - blue wire circuit editing

Node access is also required to cut and reroute signals on the silicon chip during design debugging.² This technique is commonly referred to as blue wire circuit editing or microsurgery and is typically used to verify a design change directly on the chip prior to making the changes to the lithography mask set. By doing this verification prior to taping out a new mask set we accomplish two things: We minimize the risk that the proposed mask change is incorrect, and we provide functional silicon within a few days rather than weeks, because implementing a circuit edit directly on a chip is much faster then generating a new mask set. This allows further debugging to take place on the repaired silicon.

1. For the wirebond, the interconnect to the package occurs only on the periphery of the die, whereas with the flip-chip package, the interconnects are placed throughout the die.

Figure 2 shows how design faults (a.k.a. 'bugs') are typically resolved. For two of these stages -- fault isolation and fix verification -- we need to physically access the signals on the chip. For frontside wirebond applications, this process is relatively straightforward because the signals are made accessible by removing a few microns of protective dielectric material. From the backside, however, this process is much more complex because the signal is buried below several hundred microns of silicon. Hence, in order to make these nodes visible, we must first remove the silicon above the desired node and do so without impacting the performance of the chip.

Backside signal access

Backside signal access enables the performance of silicon debugging on a chip while it is operating in the native flip-chip packaging environment for which it is designed. This is essential when the chip must be analyzed while it is operating at full speed. The objective in backside node access is to drill precision holes from the back of the chip to reach signal nodes. This objective is accomplished with a three-step process. In the first two steps the silicon is thinned, and in the third step the hole is drilled to the oxide interface. The process and methodology was engineered to minimize the throughput time for the entire process.

2. The green boxes in this debugging process indicate steps where physical access to the signals on the chip are required.

Global silicon thinning

To access signal nodes, it is not realistic to drill a small hole several micrometers square and several hundreds of microns deep through the entire thickness of the silicon. Even if this were possible, we could not measure from or connect to nodes through holes of such a large aspect ratio. The silicon is therefore pre-thinned in two steps so that the final hole only needs to be drilled through a thin section of the substrate (Fig. 3). In the first step, known as global thinning, the entire silicon substrate is thinned to a fraction of its original thickness utilizing a mechanical thinning process.

Local silicon thinning

3. Global thinning and local thinning steps used to access signals from the backside are illustrated.

In the second step, known as local thinning, silicon is thinned locally only where needed, i.e., above the selected nodes. In this way the substrate rigidity is maintained, the electrical impact to the chip is minimized and the volume of silicon removed is also minimized (therefore reducing throughput time). Local thinning is performed using a high-speed focused ion beam (FIB) anisotropic etching technique. This technique takes advantage of the high beam currents (20 nA to 30 nA) and the very reactive chemistries (such as XeF₂) available in today's FIBs. The FIB is rastered only in the area of interest, while reactive gas is delivered to the sample surface through a pair of small hypodermic size needles (Fig. 3). The reactive gas chemistry adsorbs to the silicon surface while the ion beam is rastered across the surface causing a surface etch.³ Because the etching takes place only where the beam is rastered, it is possible to mill a very precise pattern in the silicon directly over the edit or probe area.

Precision probe hole milling

In the final node access step, referred to as precision probe hole drilling, the FIB mill is used to drill a small hole in the bottom of the locally thinned section of silicon to expose the signal of interest (Fig. 4). This process is similar to the one used in the local thinning step. However, unlike the previous step where there is some margin for error, in this step the placement and size of the hole must be extremely precise in order to hit the target signal. If the edit location is missed, we run the risk of hitting adjacent lines or transistor diffusion, which will damage the circuitry. The precision and milling capability of the FIB used for this task is such that it can stop on a submicron metal line with an accuracy of better than 0.25 µm. Once the probe hole is milled, the part can be pulled out for probing, or with additional FIB processing steps, can be used for backside blue wire editing.

E-beam probing from the backside

For backside e-beam probing, a clear line of sight is needed in order to access the signal. This is done by FIB milling a probe hole through the silicon down to the node of interest. The hole is milled with tapered sidewalls to maintain a high-aspect ratio for the primary beam entering the hole and, more importantly, so the low-energy secondary electrons (SEs) can escape the hole. If the hole opening is too narrow, the SEs will collide with the sidewall, reducing the amount of usable data. The bottom of the hole must remain relatively small in order to eliminate any potential impact on the adjacent active circuitry.

4. Shown is a cross-sectional view (l) and a top-view micrograph (r) of backside e-beam probe hole. The illustration on the left shows the interaction of the primary e-beam and secondary electrons with the sample during probing.

Figure 4 shows a cross section and top view of an e-beam probe hole. Notice that the hole is really a series of holes milled in the silicon to create the necessary tapered effect. We have found that we are able to acquire very accurate signal timing information through the backside of the chip. In fact, in many ways data acquired from signals obtained through the silicon backside are much cleaner then those acquired from the frontside. This is because the grounded substrate acts as an electrostatic shield eliminating cross talk from adjacent signals and shielding against global field effects caused by high switching currents on the chip.⁴

Blue wire circuit editing process

Blue wire circuit editing is used to modify the logic or timing performance of a circuit within an IC chip. This is done directly on a packaged die in order to fully understand the impact of the edit to the modified circuit. For flip-chip mounted devices, this process is similar to that used for backside e-beam probe hole generation. However, for circuit edits, the probe hole generation is only the first step. Once a probe hole has been generated, the signal must be routed to a new connection location.

In order to route a signal across the silicon surface, the exposed signal and adjacent substrate is first covered with a blanket dielectric film that acts as an insulator between the signal of interest and the silicon substrate. The film could be deposited using an evaporator or global chemical vapor deposition (CVD) process. However, these processes would require removing the sample from the FIB editing tool, which will cause a substantial increase in throughput time. Instead, we prefer to use the FIB direct-write dielectric deposition capability available in our system, which allows us to perform the dielectric deposition step in situ.

The FIB direct write dielectric deposition process is best described as a FIB-induced CVD, where the precursors, oxygen and siloxane, are delivered locally to the sample surface through a pair of gas delivery needles, and the ion beam induces a reaction only where the beam is rastered. This process yields a surprisingly good dielectric film with typical resistivity values that range from 2 x 10¹⁴ to 2 x 10 ¹⁵ µïhms/cm for 1 to 10 V. This is quite good, considering the film is deposited using a metal ion source (gallium). The dielectric is deposited directly into the probe holes and on top of the silicon substrate area where the signal is to be routed.

5. During circuit 'edits,' a dielectric is deposited only in the connection holes and where the FIB-deposited metal is to be routed. The metal line is then routed from hole to hole on top of the dielectric across the silicon substrate.
6. In this simple circuit edit, single signal (A) is cut and replaced with a new signal (B).

Once the node and the substrate have been electrically isolated, the signals are re-exposed using FIB chemically assisted milling. To do this, we employ the same enhanced milling process used to drill the initial probe hole. After the signals have been exposed, we route the signal out of the hole and across the silicon surface to an adjacent location. This is accomplished using FIB direct write metal deposition. Once again, this is accomplished by delivering the desired chemistry to the sample surface through gas delivery needles. The material used in this case is a metallo-organic chemistry, which reacts with the ion beam to create a film on the surface. Typical resistivity values for FIB-deposited films are 100-200 ohms/cm. The final step in the circuit edit process is to complete all signal cuts isolating the original signal from the newly routed signal.

Figures 5 and 6 show an example of a simple circuit edit where a single signal (A) is cut and replaced with a new signal (B). The dielectric is deposited only in the connection holes and where the FIB-deposited metal is to be routed. The metal line is then routed from hole to hole on top of the dielectric across the silicon substrate. The cut can be seen in Location C, where the original signal is removed from the newly routed circuit. The area surrounding the newly deposited metal trace is then cleaned up using an enhanced etch process which selectively removes residual gallium and metal from the dielectric surface. This step is required because excess metal, left behind from the line deposition, and implanted gallium, left behind from imaging the sample with the metal ion source, can cause leakage from the signal to the grounded silicon substrate.

  Alternatively, if the blue wire edit is to be performed over an area that is free of any active diffusion, then it is possible to perform the edit by routing the signal directly on the field oxide. Comparatively speaking, this is a much simpler edit because it does not require routing across the silicon substrate.

7. A schematic and micrograph of a backside blue wire circuit edit over shallow trench oxide.

Figure 7 shows an example of an edit that was performed directly on the device's shallow trench oxide. Points A and B indicate the two connection locations and Point C indicates the cut locations. All the metal routing was done directly over the oxide, and the only dielectric deposition needed was directly adjacent to the invertor input at Connection Point B. This was necessary because Connection B is 0.5 µí from the invertor's transistor diffusion, and the dielectric provides an electrical isolation buffer between the connection location and the well region directly above the transistor.

Acknowledgments

The authors would like to acknowledge the outstanding development support provide by Mary Martinez, John Giacobbe, Teresa Rini, Debbie Cook and Roy Hallstein, as well as the outstanding analytical lab support provided by Steve Kirch and Leslie Serrano. Many thanks for all your help.

NOTE: Neither expressed nor implied licenses under any intellectual property belonging to Intel Corp. are provided by the contents or publication of this document.

References

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2. J. Mengailis, R.T. Post, M.W. Geis and R.W. Mountain, 'The Focused Ion Beam as Integrated Circuit Restructuring Tool,' J. Vac. Sci. Tech., B4, 176, 1986.

3. J.D. Casey Jr., A.F. Doyle, R.G. Lee and D.K. Stewart, 'Gas-Assisted Etching with Focused Ion Beam Technology,' Microelecotron. Eng., 24, 43, 1994.

4. V.R.M. Rao, 'Primary Beam Movement Effects in Electron Beam Probing,' proceedings of the 3rd Europ. Conf. on Electron and Optical Beam Testing of ICs, 1991.