Flip-Chip Packaging: Prepare for the Ramp-Up

		At a Glance
	Flip-chip packaging has been in existence for more than 30 years, but it is only now showing signs of taking off. Many are predicting that it will become prominent in the next five years. It will face a number of technical and organizational challenges in that time.

Flip-chip packaging technology has been in existence for more than 30 years, and it has evolved to encompass a wide variety of materials and techniques for bumping, attaching and underfilling. Though flip-chip has been hailed as the next interconnect method for decades, its main use has been for high-performance military and microprocessor devices (lead photo), while wirebonding has remained the predominant method for commodity parts. More people, though, are now looking to it to solve the problems associated with higher frequencies and tighter space requirements.

Since the market for it has not been large, the driving force to develop standards has been limited. A wide variety of implementations exist for flip-chip packaging, though many use some form of the controlled-collapse chip connection (C4) bumping process invented by IBM (East Fishkill, N.Y.). With the number of bump metallurgies, substrate materials and underfill materials, two seemingly similar flip-chip processes can lead to very different   degrees of success.

The 1997 National Technology Roadmap for Semiconductors speaks about the importance of flip-chip packaging in its coverage of chip-to-next level interconnect: "To satisfy the high pincount and performance requirements in the 1997 Roadmap, flip-chip will become the predominant technology for chip-to-next level interconnect. Wirebond technology will continue to evolve and will be the dominant interconnect for commodity products until flip-chip costs become favorable."¹ Flip-chip packaging has its advantages, but it is not expected to see widespread implementation until the costs of using it decrease.

It appears that the shift to area array, including flip-chip, is becoming pervasive. Paul Totta of IBM said, "Solder bump attach has really taken hold and is viewed by some people as a paradigm shift, because of where we're going with the semiconductor Roadmap. Minimum feature size is driving more and more circuits per chip, and, at least with ASICs and in microprocessors, there's a great need for area array interconnections to have enough I/O and to have the electrical environment that's needed to support these products."

The P2SC is a single-chip RISC 6000 processor designed for supercomputer applications. It has 2050 C4 bumps in an 18 x 18 mm area. (Source: IBM)

Commenting on flip-chip and chip scale packaging, Totta said, "It's only been in the past two or three years that flip-chip has really taken fire. People are really, for the first time, serious about investigating it. There may be a little confusion in the air right now because of chip scale packaging, choosing chip scale vs. direct chip attach. I don't really see that as too much of a competition at all. It's an acknowledgment that area array does indeed give the shortest path. The area array on packages and chip scale packages is simply an imitation of the area array that we've had on chips for about 20 years."

A variety of techniques

There are a variety of bumping methods for flip-chip applications. The under bump metal (UBM) must provide a transition from the die pad metal, typically aluminum, and the bump with little intermetallic stress. Sputtered aluminum-nickel-copper, evaporated chromium-copper (C4) and electroless nickel UBMs are typically used.

The bumps themselves are created in a large number of ways. High-melting (~300 ?‹C) solders, often with high lead content, are used to prevent subsequent melting at board assembly. Low-melt solders and other methods are used when the substrate cannot reliably handle the reflow temperatures of the high melt solder. Gold stud bumps have been made using wirebond equipment, but this does not lend itself to area array bumping.

One recent addition to the group of technologies that make up flip-chip packaging is polymer flip-chip packaging. Polymer Flip Chip Corp. (PFC, Billerica, Mass.) was founded to provide services in using conductive epoxy bumps instead of solder. The company has designed a one-pass printing process that has successfully placed smaller bumps in tighter patterns than typical solder processes. Bumps as small as 75 µm in diameter and 40 µm high have been printed on a 125 µm pitch. ² Printing technologies have been under development to yield 50 µm bumps on 100 µm pitches.

1. Redistribution provides a way for peripherally leaded devices to become flip-chips.

Polymer bumping also allows lower temperature processing than solder bumping, allowing a variety of materials to be used as substrates that could not withstand solder reflow temperatures. Polymer bumps can also handle thermal cycling. Though the polymer melting point is lower than that of solder, it can withstand thermally stressful environments without melting or getting brittle. Solder bumps can be more vulnerable to thermal fatigue through their brittleness than through their melting properties.

For high-temperature applications, thermoset polymer bumps can be formulated to have a high glass transition temperature. At high temperatures, these bumps would not melt and flow like solder.

Keeping Track of the Terminology One of the confusing aspects of flip-chip packaging is a widely varying set of terminologies. The list below is one attempt at straightening it out. "Flip-chip" refers only to the method of attachment or interconnection; the chip is flipped to bond the active side of the chip to the next level of interconnect. No implication is made about what the chip is attached to when the term flip-chip is used by itself. Direct chip attach (DCA) refers to the direct attachment of the chip to a circuit. The circuit is usually either a printed circuit board (PCB) or a flex circuit. Flip-chip on board (FCOB) is direct chip attached to a PCB. The term "flip-chip" is often understood to mean FCOB. DCA bypasses what is called first-level interconnect, attaching a chip to a package. Flip-chip in package (FCIP) refers to the use of flip-chip attachment into a package. FCIP is used in single-chip packages as well as multichip modules (MCMs). This is typically done when the electrical performance of wirebonded leads is inadequate, when the number of I/Os is too large for wirebonding or when there is not enough space for wirebonds to be made. This is considered to be a first-level type of interconnection. Some cases are considered to be special, such as when a single chip is bonded to a board or flex circuit. Some would call it DCA to a small board, and others would call it a large single-chip package. The Roadmap statement about flip-chip refers to it becoming the predominant method for "chip-to-next level interconnect." It refers to flip-chip in the sense described above.

Standardization and cost

Standardization and cost seem to be the hurdles to flip-chip's widespread implementation. On this subject, Wyatt Hyora, president of The Wytan Co. (Golden, Colo.), said, "The semiconductor industry recognizes that on average, 40% of costs find their home in packaging. It has also been shown that substantial cost savings result from shifting to unpackaged die. Flip-chip and chip on board technologies have been associated with cost savings with unpackaged ICs. Often, semiconductor companies do not pass along these cost savings, derived from materials and manufacturing, to the customer."

The barriers to reducing costs to the customer for flip-chip packaging do not lie with the packaging process itself, but with other practical concerns. Hyora continued, "Customers have not reaped the benefits of unpackaged die technology because of problems with testing and a lack of industry standardization."

Testing issues that affect cost for flip-chip packaging have to do with producing known good die (KGD). Testing at the bare die level is more difficult than at the packaged part level, because it requires handling the ICs in unpackaged form, and more importantly, temporary contacts to the die are difficult to reliably realize. A number of chip carrier ideas have been implemented to solve that problem for gold bumped devices.^3,4 One of them is the Die Mate carrier  developed by Texas Instruments (Dallas, Texas). Another is a TAB-based process called SofTAB, developed by Chip Supply (Orlando, Fla.).

The advantages of flip-chip

2. The Microlam PTFE-based substrate has been successfully used in high I/O single-chip package applications. (Source: W.L. Gore and Associates)

Some view the elimination of a packaging level for direct chip attach (DCA) to be one of the main advantages of flip-chip packaging. In reality, most of the steps done to package a chip in a carrier are still done when performing DCA; they are simply moved over to being a part of the board assembly process. According to J-STD-012,⁵ the main advantages have nothing to do with the elimination of a packaging level:

• Passivation films used on the chip face to control the position of the solder bump during reflow also provide high reliability at the chip level.
• The interconnection strength between the chip and package make it suitable for mechanically demanding applications.
• Flip-chips in multichip modules (MCMs) provide a very high packaged circuit density.
• Self-alignment during reflow of eutectic solder bumps allows attachment to be successful with relatively crude placement accuracy, as much as 50% off of substrate lands.
• Short electrical paths yield excellent electrical properties, with low capacitance, inductance and resistance.
• Its low profile and small footprint enable very dense applications to be realized.
• There is a degree of compatibility with surface mount technology (SMT).

Since bumps can be placed over active areas, there is no need to route chip-level I/O traces out to the edge. This would allow a die size reduction, saving some silicon cost if done in volume production. This size reduction would have to be weighed against the advantages of using a wide bump pitch.

Many bump processes allow pitches down to 200 µm. However, choosing a wider pitch can reduce routing escape problems in the next level, prevent shorting between bumps and allow more effective cleaning and underfilling. It also allows for larger bumps for more current carrying capability and reduced electromigration. A wider pitch also allows for taller bumps, which aids in cleaning, underfill, fatigue life and board flatness accommodation.

Other advantages with flip-chip processing come from redistribution. Redistribution is a wafer or die level processing step in which metal traces are routed from the die level bond pads into a new distribution (Fig. 1). With redistribution, a single substrate can be used through a series of die shrinks.

Many see redistribution only as an intermediate process to help in the conversion from wirebond packaging to flip-chip packaging. This is not its only purpose. Some may want the flexibility of using either wirebonding or area array packaging a particular device, and redistribution can afford them that flexibility. It can also be used as a fan-in or fan-out method for chips made with area array pads. That can be done to handle shrinks with area array die, or to adjust to specific packaging concerns for that device.

A number of companies are offering bumping services and are either offering or working on redistribution processes. Flip Chip Technologies (Phoenix, Ariz.), a joint venture between Delco Electronics (Kokomo, Ind.) and Kulicke & Soffa Industries (Willow Grove, Pa.), is offering both bumping and redistribution. Unitive Electronics (Traingle Research Park, N.C.), a spin-off of MCNC, is offering bumping services. Pac Tech Packaging Technologies (Nauen, Germany) is offering bumping services and equipment and is preparing to offer redistribution services as well.

Limitations

Flip-chip packaging technology has some limitations. The infrastructure for manufacturing, testing and handling of flip-chips from semiconductor vendors is not yet mature. Flip-chip packaging has existed long enough for vertically integrated companies to develop mature methods, but its limited adoption has led to a lack of standardization. Commitment to fixed bump pattern footprints and matching substrates has not yet occurred on a widespread scale.

One of the advantages of flip-chip packaging is a "relaxed" alignment requirement of up to 50% of the bond pad size. However, when the ball pitch is 250 µm and the bond pad diameter is on the order of 100 µm, this requirement is not very relaxed. Also, visual verification of bump placement on the substrate is not easily done, making die placement accuracy very important. Vision system vendors have been called upon to help solve that problem.

Another placement accuracy problem is the possibility of the die shifting position between the time it is placed and the time that the solder is reflowed. Alphasem AG (Berg, Switzerland) has added an in-line reflow oven to its SL9002 FC machine to minimize the time and handling between those two steps.

The coefficient of thermal expansion (CTE) mismatch between silicon and most substrates causes such limitations as thermal cycle fatigue failure of solder and thermal shock failure. Heat dissipation is also limited without an underfill. Strain level in the solder is reduced with the use of underfill materials, but that introduces a significant throughput reduction and an inability to rework after underfilling. Camelot Systems (Haverhill, Mass.) is developing a multihead dispense system as one way to improve throughput in its underfill dispense equipment.

Also, material properties of underfill materials can vary over the space of a day or a shift. Most underfilling is done after the chip is attached, by applying the material at the edge of the die and allowing it to wick underneath. Variability in material properties leads to large variations in the process. Asymtek offers a fluid management system in its Millennium series of dispense systems designed to adjust to viscosity changes over time. It also uses a piston pump to avoid grinding filler particles, which can affect viscosity.

Highly controlled dispensing for underfilling is also required, not only to control the process but to minimize waste and drip. Camelot's 3600 dispenser offers a rotary pump with a self-sealing cartridge designed to provide ?}1 mg accuracy with no drip. Asymtek's system is designed to dispense a programmed amount of material with a 1% tolerance over long production runs.

Another problem associated with flip-chip is alpha particle-induced soft errors in the chip. Most ordinary lead solders contain daughter elements that emit alpha particles. Low lead content solders are being examined to reduce the use of lead, which also would have the benefit of reduced alpha emissions. Low alpha lead can be found, though, for those who want to use lead solders and keep soft upsets down.

Make Standards Sensible One of the largest potential problem areas with a major shift to flip-chip packaging is standards. Flip-chip is not likely ever to be standardized unless all semiconductor companies worldwide join forces and cease to compete in design and technology. Chip-scale packages are a means of providing such standards. However, at the moment, they are also in flux, with a variety of pitches and ball sizes being used. Though vertically integrated companies can choose whatever pitches they see fit, sensible standards must come into play when multiple companies are involved in the production of an IC product. a. A standard test socket pitch of 0.5 mm provides capability for 1.0 and 0.707 mm and other multiples of the base pitch virtually for free. Suppliers of area array packages can supply packages with virtually any pitch; normally it is a simple artwork and soft tooling change. Those most affected by a proliferation in pitches are the ones who have to make the test sockets, which are typically hard tooled. Providing test socket capability for all the pitches available now can become very expensive. Testing operations can charge extra to handle them, but that is in direct conflict with the drive to keep cost per I/O down. In the past, peripherally leaded devices employed what has been called "the 80% rule" to determine lead pitch shrinks. Thus, a 1.0 mm pitch would be followed by a 0.8 mm pitch, and so on. That rule worked well for peripherally leaded devices, but it was a completely arbitrary convention. Presently, people seem to be blindly using the 80% rule concept for area arrays as well. However, that rule does not take full advantage of the opportunity offered by area array geometry. Working from a single established base grid pitch would provide automatic compatibility between all pitches, providing coherent links between semiconductor package, testing, socketing and substrate design and manufacture. The canonical pitch appears to be 0.5 mm, which will allow placement of all I/O under the die for virtually all memory and microprocessor chips in use today. When you consider the routing and ball size changes that go with pitch changes, there is very little difference, in terms of I/O capacity, between 0.65 mm, 0.75 mm, 0.8 mm and the 50% depopulated 0.5 mm grid, which yields a 0.707 mm pitch (Fig. a). So, why ask an assembly and testing house to handle all three, in addition to 1.0 mm and 0.5 mm? A basepitch of 0.5 mm that can be depopulated is already called out in JEDEC MO-195 and can serve the foreseeable packaging needs of almost all ICs at or near chip size. The international standard that serves as a rallying point for this coherent approach to pitch standards is International Electrotechnical Commission (IEC) Publication 97, titled "Standard Grids for Printed Circuits." It is based on a 0.5 mm pitch. I believe that it would be a good starting point for future standards.

Substrates

Flip-chip in package (FCIP) is expected to grow more rapidly than DCA in the next five years, and it requires suitable substrates to be successful. Improvement in substrate characteristics is a prominent theme in the 1997 Roadmap goals. Pat O'Brien of Amkor said, "DCA on the system board has not found widespread adoption above 50 leads. For die with larger pincounts, adoption of FCIP is expected to grow more rapidly over the next five years. The single- or multichip implementation has advantages over DCA because it localizes high-density/high-cost substrate technology, DCA is not reworkable and there is some resistance to implementing underfill on SMT lines. As the buildup substrate infrastructure matures, prices should fall rapidly and allow for more widespread adoption of the flip-chip BGA package."

A variety of substrates have been used in flip-chip packaging. Ceramic substrates are used to handle the large amounts of heat that high I/O flip-chip devices generate. Regular PC boards and flex circuits act as the substrate in DCA applications. Organic laminate substrates are also being used, and there is a push to develop them further.

W.L. Gore's (Eau Claire, Wis.) Microlam substrate material is a PTFE composite designed to match the CTE of copper. The company said it built substrates with up to 1800 off-package I/Os using Microlam (Fig. 2).

Alpine Microsystems (Campbell, Calif.) has brought back the silicon substrate concept with its recently introduced "micropallet" technology. A piece of silicon is used as the substrate, and simple silicon processing technology is used to create routing in it. Since the chip and substrate are both made of the same material, there is no CTE mismatch.

Projected needs

According to the 1997 Roadmap:¹ "Size, weight and performance-driven products will need flip-chip interconnect with area array I/O at a pitch of 250 µm or less. This interconnect approach will require compatible underfill and substrate technologies to be available at the necessary performance and cost." Flip-chip implementation is being called upon to increase and improve.

The Roadmap continues: "Material, process development and metrology technology improvements will also be required to support flip-chip implementation. Flip-chip interconnect technology at area array pitches < =250 µm will put extreme pressure on substrate density for I/O escape beneath the chip site. Substrate redesign is usually necessary to accommodate flip-chip interconnect chip shrinks."

Also, the use of eutectic tin-lead solders is being sought to allow the use of organic substrate. The classic C4 process uses a high-melting (300 ?‹C) 97Pb-3Sn solder to maintain the integrity of the flip-chip bond during subsequent processing. The high temperatures required to reflow that solder would degrade the substrate.

Conclusion

Flip-chip packaging has been in use for more than 30 years, but it has only now beginning to show promise for widespread use. Standardization of the process seems to be the first hurdle. After that, sub-250 µm pitch processes will have to be developed. Low alpha solders and organic substrates will have to be improved to provide costs that are attractive enough to make flip-chip packaging widespread.

References

1. The National Technology Roadmap for Semiconductors, 1997 Edition, Semiconductor Industry Association.

2. R.H. Estes, "Flip-Chip Packaging with Polymer Bumps," Semiconductor International, February 1997, p. 103.

3. T. Carter, E. Craig, "Known Good Die Comes of Age," Semiconductor International, October 1997, p. 175.

4. J. Baliga, "TAB-Based Process Produces Known Good Die," Semiconductor International, December 1997, p. 40.

5. J-STD-012, Joint Industry Standard, Implementation of Flip Chip and Chip Scale Technology, The Institute for Interconnecting and Packaging Electronic Circuits, January 1996.