Challenges for 300 mm Plasma Etch System Development

		At a Glance
	Equipment suppliers not only face challenges in scaling etch systems to process 300 mm wafers, but they must address the requirements presented by new materials, the need for novel process and equipment control technologies that will permit processing down to 0.13 µm features and a heightened sensitivity to environmental concerns.

The transition to 300 mm wafer size will provide etch system suppliers with technical and economic challenges, which are driven as much by the expectations of chip manufacturers as by equipment suppliers' own technology roadmaps. This transition will require the creation of a new generation of tools and significant advances in process technologies.

It will also impose new requirements ranging from economic to environmental. This article discusses new requirements for 300 mm etch systems and introduces several technologies for achieving them.

Productivity challenges

A 300 mm wafer allows 2.4-2.7 times more die per wafer, higher wafer perimeter efficiency, higher output per wafer start and a 25-40% reduction in per-die cost.¹ However, to stay on the 25-30% manufacturing cost learning curve, the transition must be accompanied by feature size shrinks to 0.18 µm (180 nm) and below, increased yields and improvements in equipment productivity with an average system overall equipment effectiveness (OEE) of 60%. According to a SEMATECH (Austin, Texas) report, incoming plasma etch equipment demonstrates an industry average of 28% OEE. Efficiency improvements will be achieved by reducing unscheduled downtime, test wafer consumption, and installation and setup time, while maintaining high device yields.

Reducing unscheduled downtime is made possible by many factors, including designing the system to industry specifications such as SEMI S2 and S8 guidelines for equipment safety and ergonomics, respectively. Additionally, systems will benefit from on-board fault-detection, failure diagnostics and advanced equipment and process control features. On-board algorithms, which examine and correlate multiple sensor signals simultaneously -- such as multivariate fault detection, fault classification, adaptive equipment and process control -- will be employed to reduce per-die cost. Unscheduled downtime may also be reduced by implementing a strictly SPC-based total preventive maintenance (PM) program.

We have supported the reduction of test wafer consumption during start-ups and at PM by using in situ sensors to characterize the process chamber and establish a baseline for future calibrations. This chamber fingerprint is then available for matching parameters during subsequent start-up, qualification and PM steps, thereby reducing test wafer consumption and minimizing downtime.

The 300 mm generation will see a shift from controlling equipment parameters to improving process control. Advanced sensors and algorithms will reduce process variance and maintain high yields with the narrower process windows. For instance, adaptive process control methods will allow systems to self-tune, compensating for effects such as chamber aging and incoming product variations.

Equipment modeling

Approximately 75% of today's wafer fab costs are due to capital equipment, and there is increasing pressure from chip manufacturers to contain system price and to shorten equipment development time. New products must span at least two device generations and, on average, three to four generations. For 300 mm, this means system designs must address the requirements of 0.18 µm, 0.15 µm (150 nm), 0.13 µm (130 nm) and, possibly, 0.10 µm (100 nm) technologies. To manage these challenges, efficient, cost-effective design strategies are needed.

Traditionally, prototypes are developed and tested based on good ideas for solving process-related problems -- such as etch rate, selectivity, uniformity and particles generation -- by modifying an existing equipment design. This approach to equipment development relies on hardware prototyping, which is designing, manufacturing and testing before the solution is determined to be effective. This traditional method is limited since it verifies only a very narrow range of design possibilities while leaving a large parameter space untested.

In addition, the costs of extensive prototype hardware testing are now prohibitive. For example, the cost of a two-week, single-etch application marathon beta hardware test using 1000 300 mm silicon wafers judiciously (reworking and recycling) can run upwards of $1.25 million. This expense is in addition to the year-long investment in concept and feasibility, hardware development and prototyping, engineering resources and test wafers used in qualifying multiple applications.

1. Lam's 300 mm TCP etch reactor design was characterized and optimized by computer modeling and diagnostics. Validation of the plasma modeling is evident in the good etch uniformity obtained on 300 mm wafers as shown by the above etch rate profiles.

For 300 mm development, advanced process equipment modeling (PEM) is a viable solution based on the needs for a short time-to-market cycle and reduced development costs. PEM has proved to be one of the most cost-effective methods of developing and testing prototype systems. ^2,3 We have used PEM simulation combined with diagnostic tools, such as Langmuir probes, and are able to reveal the effects of TCP power, chamber pressure, aspect ratio and coil configuration on plasma properties such as plasma density, plasma potential, electron density and plasma uniformity. The validation of the plasma modeling is evident in the good etch uniformity obtained on 300 mm wafers (Fig. 1).⁴

Plasma source technology

Meeting technology requirements for 300 mm plasma etch will involve developing a robust source that can scale to 300 mm and meet requirements of the 0.18 µm, 0.15 µm and 0.13 µm feature size generations. With tighter specifications at smaller feature sizes, an inherently uniform source technology will provide a significant advantage. Not only does the plasma need to scale seamlessly from 200 mm to 300 mm, it must also etch increasingly smaller feature sizes with extreme precision and tight control. The 1997 SIA Technology Roadmap identifies the high-density sources (ICPs, ECRs and helicons) operating at low pressures as the technologies of choice to meet next-generation requirements.

High-density plasma sources (HDPS) operating at low pressure address the needs of the sub-0.25 µm (250 nm) era for improved etch rate, selectivity to both mask material (organic and inorganic) and underlying layers, and reduced damage (physical and electrical). High etch rates of films and high selectivity to mask material are only possible with sources that provide high-density, low-energy ions, which allow for an ion-assisted surface chemical reaction and ensure a high etch rate with reduced sputtering of mask material. The reduced-pressure operating condition also ensures anisotropy of low-energy ions.

Loading effects

The move to 300 mm increases the macroscopic, microscopic and aspect-ratio dependent loading effects. With the increase in substrate diameter from 200 mm to 300 mm, the etch area increases by 2.25 times. Given the same pattern density, there is more etch material in the reactor. If the optimized etch parameters of a 200 mm process -- such as gas flow, applied bias, pressure and temperature -- are ported without change to a 300 mm chamber, the macroscopic loading effect will prevent optimized etch results. The first-order impact is a significant drop in etch rate because of feedstock gas depletion.

The microscopic loading effect is exacerbated by the smaller feature sizes of 0.18 µm and 0.15 µm. The same size features etch more slowly in densely patterned regions than in sparsely patterned areas. Similarly, the isolated feature profile is more sloped than the profile of densely patterned features. Microscopic loading is even more severe center-to-edge when the wafer diameter increases.

Aspect-ratio dependent etch (ARDE) rate has an added impact on wafer throughput. The ARDE effect results in high-aspect features etching more slowly than low-aspect ratio features; the rate decrease with depth is commonly referred to as RIE lag. The throughput advantage from etching thinner intermetal dielectric films at smaller feature sizes is negated by the ARDE effect, and longer etch times are required to clear material from contact and via depths. The effect is compounded at 300 mm since longer main and overetch time is required to account for center-to-edge non-uniformity.

The longer overetches increase mask erosion and CD loss. The challenge at sub-0.25 µm features, then, is the requirement to optimize the 300 mm processes with new chemistries, pressures and applied bias to increase etch rates for higher throughput despite high-aspect ratio loading effects.

Oxide etch

Dielectric etch is by far the most challenging etch technology at 200 mm and promises to be no less so at 300 mm. It forms the largest etch application market relative to silicon, metal (Table 1)⁵ and strip.

The challenges in 300 mm oxide etching are the requirements for tighter process specifications commensurate with shrinking feature size (Table 2), intrinsic technology hurdles, new applications -- such as dual damascene for use in copper applications -- and the ability to etch new dielectric materials for faster devices.

Achieving I300I's rigorous 0.18 µm (180 nm) etch process specifications shown above will further challenge suppliers in developing 300 mm systems.

Maintaining high selectivity to the mask layer and underlying substrate while maintaining high etch rates at larger aspect ratios will be difficult. The selectivity of oxide to resist is critical in maintaining low CD bias (±5% feature size) and high CD uniformity across the 300 mm substrate. The required selectivity of oxide to resist at 0.18 µm feature size is at least 15 to 1. Similarly, the required selectivity to underlying substrate films, such as polysilicon and polycide, is 50 to 1. Also, aspect ratios for DRAM applications will increase from 5.5 at 0.25 µm feature size to 6.3 at 0.18 µm.

The high resist selectivity requirement is a challenge, given that current photoresist selectivity performance is barely in the double digits. High-density, low-pressure reactors have maintained high etch rates by operating at high power and, hence, at high ion energybombardment(>80 to 100 eV). The high-energy physical bombardment is required for sidewall passivation by polymer to ensure good anisotropy and vertical profiles. Most etch processes using perfluorocarbon chemistries operate at a highly balanced critical polymer point, where polymer generation is just enough to ensure high substrate selectivity without excessive mask erosion. Any deviation from the critical polymer point results in complete etch stop. This phenomenon has been the bane of high-density oxide etchers and has resulted in the frequent use of in situ plasma chamber clean. Solutions to resist erosion and loss of photoresist selectivity range from optimizing etch chemistries to adding a sacrificial heated silicon source within the chamber to capture excessive flourine.⁶

New etch applications, such as dual damascene, and new materials, such as low-k dielectrics, form additional development needs at 300 mm. One of the requirements for dual damascene evolves from incorporating copper as a low resistivity interconnect as part of the multilevel metal integration scheme, since copper etch byproducts are non-volatile.⁷ The difficulty in etching damascene is the high-aspect ratio requirement of >8:1. Also, depending upon the type of 0.18 µm process integration scheme adopted for dual damascene, the selectivity requirement of oxide to nitride is as high as that required in self-aligned contact (SAC) etch.

Low-k dielectrics find application in interlevel dielectric (ILD) to reduce parasitic capacitance and cross talk. At 0.18 µm and smaller feature sizes, low-k dielectrics (k <3.0) -- such as (CYCLOTENE*5021 (BCB) and SiLK Semiconductor Dielectric)⁸ and polyarylene ether (PAE-2⁹ and Flare 2¹⁰) -- will be required. The underlying selectivity mechanism of the etch process relies on the absence of sputtering and ion energy usually less than 100 eV. The etch chemistry is oxygen-based, meaning that the reactions are principally combustion in nature. Although the adoption of low-k dielectrics has the potential of removing some of the thermal oxide-based etch difficulties, it introduces new problems, such as isotropy and undercut.

2. TCP 9100 etch capability for low-k dielectrics, Dow Chemical's CYCLOTENE*5021 (BCB), at low pressure (12 mT) in O2/C2F6/Ar chemistry, is demonstrated.

To understand the impact of this new etch technology and determine solutions for the 0.18 µm generation, Lam is participating in a SEMATECH-sponsored project to benchmark low-k dielectric etch. A TCP 9100 system is currently installed at SEMATECH, and a series of etch design experiments will be run to determine process windows for a variety of novel low-k dielectrics. Current capability of etching using Dow Chemical's CYCLO-TENE*5021 (BCB) was demonstrated on the TCP 9100 etcher (Fig. 2).

Polysilicon/polycide etch

Polysilicon and polycide gate technology will still dominate at 300 mm. New forms of gate technology such as metal gates are expected, given that the gate oxide will thin to 2 nm for 100 nm gates, thereby reaching the limits of tunneling physics. The change in isolation technology will also form a substantial part of the etch business since LOCOS and poly-buffered LOCOS will now give way to shallow-trench isolation (STI).¹¹

3. This WSix/poly multistack gate etch in the 300 mm Lam TCP process module demonstrates good control across the wafer and over severe topography, preventing notching at the silicide-poly interface.

Silicide will still be required at 300 mm, given that the demands for gate electrode sheet resistance (4-6 ohm/square) remain unchanged for future generations of feature sizes. Silicide gate etching will continue to rely on the ability to etch the multistack gate layer with good control across the wafer and over severe topography and to prevent notching at the silicide-poly interface, as demonstrated in the 300 mm TCP etcher (Fig. 3).

Isolation for sub-0.25 µm feature sizes on 300 mm will require STI technology. Transistor packing density requirements will drive the STI etch specifications to trenches with steeper sidewall angles and rounded corners.

Dual-doped (p⁺ and n⁺) gate technology on the same substrate will meet the demand for better control on transistor threshold voltage. Because the etch rates of the highly dual-doped gates are significantly different, they will impact gate profile. The solution to the dual-doped gate etch lies in optimizing the process recipe to avoid undercutting the higher etch rate material during long overetches.

At smallerfeaturesizes (<0.10 µm), device physics will compel integration of metal gate technology into CMOS technology. These novel gates will require new etch chemistries to assist in controlling the chemical nature of metal etch to preserve anisotropy and maintain good CD control. New gate dielectrics such as oxynitrides and nitride with a high dielectricconstant(k>7) will also be required to overcome the tunneling currents in thin oxides. The 300 mm poly etch challenges are to design processes that endpoint reliably on the new dielectrics and prevent punch-through effects during long periods of overetch.

Issues such as pattern density and the percentage of open area will now be critical to defining a robust gate poly process. A process that may be highly selective in DRAM manufacturing would not necessarily give the same results in etching a microprocessor chip because of the impact of pattern-density-related loss of selectivity.¹²

Preserving the gate dielectric material is a significant challenge during gate etch of small feature sizes and on large-diameter wafers. The ability to define a gate on a 2 nm gate oxide without punching through the dielectric requires very high selectivity to the oxide without sacrificing the ability to remove polysilicon residue and stringers. The dielectric thickness at 0.15 µm feature size is just 20-30Å (6-10 monolayers thick). The process specifications require no more than a 5Å loss -- 1.5 monolayers thick -- across a 70,686 mm² surface.

4. This 300 mm wafer poly line/space etched in the Lam 300 mm TCP poly etch system shows a high degree of profile control (89 ° between center to edge features and good microloading control.

Such tight specifications require selectivity >150:1 during the main etch process to prevent punch-through of the gate dielectric and an even higher overetch selectivity in excess of 250:1 to clear residue and stringers. Current poly etch chemistries have demonstrated this potential but require a high degree of optimization and a robust process window. A high degree of profile control (89° between center to edge features and good microloading control is seen in 300 mm poly wafers etched in the Lam 300 mm TCP process module (Fig. 4).

Metal etch

The 300 mm metal etch market will be dominated by traditional aluminum interconnect and its variations, i.e., TiW/Al/optional TiW cap, Ti/TiN/Al/optional TiW cap. Tungsten etchback and tungsten-based interconnect etch will still be a sizable portion of the 300 mm etch applications.¹³

Metal etching at 300 mm requires:

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• High etch rates(>1000 nm/min)
• Highuniformity(<9% 3s)
• High selectivity to the maskinglayer (>4:1) and intermetal dielectric(>20:1)
• Minimal microloading(<8%) at any location on the wafer
• No damage
• Low contamination
• Fast and clean resist strip
• Good corrosioncontrol(>24 hrs)

Metal etching is largely chemically driven, and etch reactant concentration at the wafer surface, such as chlorine, largely determines the etch rate and uniformity.¹⁴ The concentration of etchant, free radicals and neutrals, and etch byproducts is not uniform, given the enhanced depletion of the etchant in the wafer center and increased etchant concentration at the wafer edge because of back diffusion. This nonuniformity makes etch rates at the wafer periphery higher than at the center, resulting in high center-to-edge nonuniformity that is compounded by the longer 300 mm diameter. Plasma uniformity distribution across the 300 mm wafer increases the problem if the edge diffusion effect is not optimized.

The solution to etch uniformity problems is to use a barrier to prevent back diffusion of etchant species at the wafer periphery. The current trend has been to implement uniformity rings that reduce back diffusion.

Improved etch uniformity translates to better CD uniformity. This correlation of etch to CD uniformity may not hold in all cases. Some attempts to improve etch uniformity result in
compromising CD uniformity. Long overetches are usually done to clean metal etch residue from high-aspect ratio features and to solve for edge-induced nonuniformity. However, large overetches may result in mask erosion and compromise CD bias and uniformity. The current trend of using thinner DUV photoresist, which cannot withstand long overetch, as the mask layer and the requirement for long overetches to improve uniformity results in severe resist erosion. The challenge is to optimize long overetches for uniformity control with minimal DUV mask erosion while maintaining good CD and feature profile.

Device damage from electrical charging will continue to be another challenge. The device circuitry is connected to even larger antennas, given the 180% increase in interconnect lengths in 300 mm wafers over 200 mm wafers.¹² The large charge collector area makes the devices highly vulnerable to damage. Plasma non-uniformity in excess of 20% of ion-electron spatial imbalance will result in device damage. However, plasma non-uniformity <20% may not be the only reason for device damage, and, instead, pattern-dependent device charging may account for the failures. Pattern-dependent charging can occur in a uniform plasma and is caused by the difference in isotropy of electrons and ions crossing the plasma sheath to the wafer surface.^15,16 Extensive analysis and fundamental understanding of the process and damage issues are required to address the challenge from electrical charging.^17-19

Reduction of PFCs

Equipment suppliers will be expected to reduce emissions by 50% of greenhouse gases (PFCs) for 300 mm systems to comply with a 1996 voluntary agreement between the EPA and chipmakers. For etch, this is an enormous challenge, given the larger volume of 300 mm chambers and hence the increased flow requirement for PFCs, which are integral to the oxide etch process. This requirement will involve studying current emissions and characterizing the impact of all variables, optimizing process parameters, re-searching alternative chemistries and developing methods for recycling and recovery of PFC compounds.

Conclusion

In addition to scaling etch systems and devising new technologies to process 300 mm wafers, equipment suppliers will be challenged by new materials, the need for novel process and equipment control technologies that will permit processing down to 0.13 µm features, and a heightened sensitivity to environmental concerns -- among other requirements. The challenges are clear, though formidable, and the development solutions are coming. This will be an intense and interesting transition period.

Acknowledgments

We would like to acknowledge the contributions of the following individuals from Lam Research Corp., who provided support for this article: May Su, Jay Maille, Joel Cook, Ken Krieg, Neil Benjamin, Roger Patrick, Ian Morey and Ken Yasuda.

References

1. G. Lee, "Equipment Suppliers Make 300 mm Dream a Reality," Future Fab International, p. 61.
2. W. Collison, M.J. Kushner, Applied Physics Letter, vol. 68, p. 903, 1996.
3. V. Singh, "Model-base equipment design for optimized plasma processing," Solid State Semiconductor, June 1997.
4. W.Z. Collison, T.Q. Ni, M.S. Barnes, "Studies of the Low Pressure Inductively-Coupled Plasma Etching for a Larger Area Wafer Using Plasma Modeling and Langmuir Probe," JVST A 16(1), Jan./Feb. 1998.
5. Dataquest, "Semiconductor Wafer Fabrication Equipment Forecast," Dec. 97.
6. P. Singer, "The Many Challenges of Oxide Etching," Semiconductor International, July 1997, p. 109.
7. Y. Morand, "Copper Integration in Dual Damascene Architecture for Sub-Quarter Micron Technology," VMIC 1997, p. 75.
8. CYCLOTENE*5021 (BCB) and SiLK by Dow Chemical Co.
9. PAE-2 is a trade name of Schumacher, Carlsbad, Calif.
10. Flare 2 is a trade name of Allied Signals, Sunnyvale, Calif.
11. Dataquest, "Semiconductor Wafer Fabrication Equipment Forecast," Dec. 1997.
12. The National Technology Road-map for Semiconductors, 1997 edition.
13. Dataquest, "Semiconductor Wafer Fabrication Equipment Forecast," Dec. 97.
14. . D. Beale, S. Siu, R. Patrick, Journal of Vacuum Science and Technology, to be published.
15. K. Hashimoto, Japan Journal of Applied Physics 32, 6109 (1993).
16. K. Hashimoto, Japan Journal of Applied Physics 33, 6013 (1993).
17. R. Patrick, S. Siu, P. L. Jones, International Symposium on Plasma Process-Induced Damage, May 1997.
18. R. Patrick, P. L. Jones, International Symposium on Plasma Process-Induced Damage, May 1997.
19. V. Vahedi, N. Benjamin, A. Perry, International Symposium on Plasma Process-Induced Damage, May 1997.

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Sanjay Tandon is the 300 mm Etch product manager at Lam Research Corp. Previously, he was customer technology manager for the company's Conductor Etch Division. He has 12 years of experience in CMOS process integration and device physics. He received a bachelor's degree in physics and computer science from Randolph-Macon College and a master's degree in electrical engineering from North Carolina State University.

E-mail:sanjay.tandon@lamrc.com

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