Fab Eliminates Yield Loss due to Manual Wafer Handling
Wafer scratches can significantly contribute to probe yield loss in mature fabs.
Laura Peters, Senior Editor -- Semiconductor International, 6/1/1998
A mature fab known for low cost, low cycle time manufacturing can suffer significant yield loss because of a number of manual wafer handling procedures. Texas Instruments (TI, Dallas, Texas) was able to automate wafer handling in a mature fab that was experiencing a 7% yield loss that was due to wafer scratches caused by manual handling. The company effectively eliminated manual handling in the photolithography and plasma areas of the fab, reducing resist-related scratches by 83%. The improvements in yield helped fund the second and third phases of the program, automating wafer handling throughout the fab.
TI first estimated yield loss that was due to manual wafer handling by determining the average number of new scratches at each of eight inspection steps in the process. When physical defects on wafers were detected and analyzed, a 7% yield loss was estimated. Approximately 95% of the scratches were randomly located on the wafers, indicating that the vast majority were caused by human error and not equipment-related problems. By tabulating each manual transfer of a wafer, the group found that a total of 535 individual manual wafer transfers took place per lot, averaging 22 wafer handling procedures per wafer. Using an average of 3% die affected per scratch, a 7% yield loss was confirmed. By categorizing the scratches by type of handling performed (Fig. 1), TI determined that the highest percentage was performed in verifying lot numbers on the wafers (28%). When broken out by fab area, 51% of the handling took place in the critical photolithography and plasma processing sections, which were then selected for the first phase of automation.
The company formed quality improvement teams (QITs), each consisting of 10-15 people to address automation of the photo and plasma areas on each of the fab's three shifts per day and A and B shifts on the weekends. Comprised largely of manufacturing
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Fig. 1. Twenty-eight percent of handling steps were performed to verify lot numbers on the wafers. |
Another example involved the handling of wafers in and out of a batch metal etch tool with special leading requirements. Pilot wafers are typically added to round batch sizes to 12, 16 or 18 wafers. Special steps are also required for particle monitoring and statistical process control (SPC), reactor conditioning and endpoint checks following maintenance. A four-cassette wafer sorter was used to accommodate these complex recipe changes. Throughout the course of the project, unnecessary wafer handling procedures were eliminated either by restructuring the process, or by making process and equipment enhancements suggested by yield enhancement or process engineers and technicians.
To measure the success of the project, the QITs tracked the number of vacuum pencils removed from the fab twice a month and the average number of scratches detected each month. Scratches were categorized by resist scratches, in which a feature was disturbed by resist fragments before etching, which subsequently blocked the etch, and non-resist scratches, in which debris blocks the etch. After implementing phase-1 actions, resist-related scratches were reduced by 83% (Fig. 2).
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Fig. 2. By replacing manual with automated wafer handling and optimizing procedures, resist-related scratches were reduced by 83%. |
The results of this project were reported by Richard Guldi, et al., in the 1997 proceedings of the IEEE/SEMI Advanced Semiconductor Manufacturing Conference.
