LSI Logic Announces G12 0.18 µm Process
Staff -- Semiconductor International, 6/1/1998
LSI Logic (Milpitas, Calif.) announced the G12 Series, 0.18 µm (180 nm) process technology. Prototype design will start from the fourth quarter of 1998, with the new Gresham Fab to ramp up from the second quarter of 1999. In Japan, the firm plans to begin accepting orders from mid-1998.
The G12 series is a 0.18 µm process with an effective channel length (Leff) of 0.13 µm (130 nm). The number of usable gates on a 20 mm square chip is up to 26 million. Compared to the older G11 process technology, the new technology offers about triple the number of gates per millimeter.
The new process technology uses shallow-trench isolation (STI) to isolate devices, and the wiring pattern is a six-layer aluminum damascene (seven layers, counting the bottom-most local wiring layer). The contact pitch is 0.63 µm, and Al-CMP is used for Al embedding.
The interlayer dielectric is a low-k film, and while the material has not been disclosed, the performance has been given as k = 3.0 or lower. The firm did not use Cu wiring because "Cu requires a dedicated line, and it just didn't justify the cost." The firm instead made the decision to move into the 0.18 µm generation by combining Al metalization with low-k films.
