Configurable 200 MHz DSP Architecture Demonstrated

Staff -- Semiconductor International, 6/1/1998

Infinite Technology Corp. (ITC, Richardson, Texas) and Air Force Research Laboratory (Dayton, Ohio) demonstrated the feasibility of a configurable digital signal processing (DSP) architecture on 0.35 µm (350 nm) CMOS technology. The result of the Small Business Innovative Research Phase I project demonstrated a 200 MHz multiplier-accumulator (MAC) using what the company calls a reconfigurable interconnect fabric.

The purpose of the architecture is to enable a fast, custom design of a DSP coprocessor to the needs of the specific problem, rather than fit a standard DSP chip to the problem. He said, "I like to use the analogy of a software-driven design approach, where you let the algorithms of your problem, which is at a higher level than going down and working at the logic and transistor level, set the right type of signal processing data flow architecture." A DSP design can be created within a few days.

The term interconnect fabric refers to the way that the execution units, or intellectual property (IP) cores, are optimized to allow them to be connected in a modular fashion. Veal continued, "They can be connected together, visualized like Lego blocks. The interconnect fabric is tuned to optimize performance in the semiconductor process, in terms of making sure you have enough drive strength to drive the right data bus structure and having the right clocking structure set up to support that." The interconnect fabric is designed to provide an immediate path from design to silicon fabrication.

One of the future plans for the architecture is to allow the creation of very long instruction word sets. With a custom instruction set using very long instruction words, it is said to be possible to drive billions of operations per second on current silicon technology.