Surface Contamination Control Using Integrated Cleaning

		At a Glance
	The benefits of integrated cleaning with low temperature deposition were studied, with a special focus on epitaxial silicon precleans. Three AHF-vapor cleaning processes were examined. In all three, the wafer was first exposed to a gaseous mixture of AHF, HCl, H2O and N2. In the first process, the vapor step was followed by a DI rinse and spin dry. In the second process, the vapor step was followed by a reactive rinse, a second DI rinse with no AHF gas and a spin dry. In the third process, the vapor step was followed only by the reactive rinse and a spin dry with no final DI rinse.

Much has been written and presented over the past 10 years with respect to integrated cleaning. In a broad sense, the term integrated cleaning can encompass any process system that includes a contamination-removal step either before or after the primary process sequence. In situ hydrogen pre-bake before epitaxial deposition, in situ etch residue removal following photoresist ashing, integrated brush cleaners for slurry removal following CMP and pre-sputtering before metal deposition could all be considered examples of integrated cleaning. However, for the purposes of this discussion, integrated cleaning will be more narrowly defined as the direct transfer of a substrate from a surface cleaning process to the subsequent process step and, in this sense, will be distinguished from in situ cleaning. With this narrower definition in mind, the main purpose of integrated cleaning is to minimize substrate surface recontamination by avoiding ambient exposure and by reducing queue time.

Historically, processes requiring precleans, such as oxidation, LPCVD and diffusion, have been batch processes. In order to match the throughput of these batch thermal processes, batch cleaning processes have been utilized. Batch cleaning has almost exclusively used wet chemicals (RCA clean) and DI water rinsing. Integrated cleaning has not generally made sense in this context of batch processing. Also, since the thermal processes are generally vacuum-based, the use of atmospheric cleaning processes with DI water rinsing raises barriers to integration. While integrated cleaning is usually considered a single-wafer issue, there has been at least one case in which a batch vapor cleaning process has been integrated to a batch vertical furnace.¹ However, consideration of integrated cleaning has mainly been linked to the move toward single-wafer, vacuum-based thermal processing.

Integrated, single-wafer cleaning has been contemplated and tested since the late 1980s.² With the introduction of single-wafer anhydrous HF (AHF)-vapor, UV/ozone, chemical downstream etch (CDE) and other dry processes, integrated cleaning has become a viable approach to surface contamination control. One focus has been on an integrated process for building the gate stack: surface clean, followed by RTO gate oxidation, followed by RTCVD polysilicon deposition. ^3-5 Work has also been directed toward low-temperature, single-wafer epi deposition, ^6,7 as well as newer applications, such as selective hemispherical grain silicon formation. ^8,9 In each of these cases the goal is to produce a clean silicon surface, free of native oxide and other contaminants, and transfer it to the thin film growth or deposition chamber without recontamination by avoiding ambient exposure.

While these approaches have focused on the removal of "chemical" contaminants, they have largely avoided the issue of particulate contamination removal. While cluster-compatible, single-wafer particle removal technology is currently available,¹⁰ it is likely that the early implementation of integrated cleaning in production will include an initial ex situ particle-removal step prior to the cluster system.

Fig. 1. Vacuum deposition platform with integrated cleaning module. 5-7

Two approaches to integrated, single-wafer cleaning have been taken. In one approach, process technologies for cleaning the wafer surface in a dry, vacuum environment have been developed and directly integrated to the vacuum platform for oxidation and deposition.^{3 ,4,9} Cleaning processes performed in the dry vacuum environment generally employ low-pressure AHF with alcohol vapor in addition to UV/ozone and UV/Cl₂. In another approach, existing technology for single-wafer, AHF-vapor cleaning has been integrated to the thin film vacuum deposition, as shown in Figure 1.^5-7 This vapor cleaning system employs AHF-vapor at near-atmospheric pressure and also em-ploys an in situ DI rinse with spin dry. The limitations to integration associated with water rinsing are overcome with the use of a vacuum loadlock transfer chamber.

Experimental studies

The vapor cleaning system shown in Figure 1 allows the wafer to be exposed to any combination of gaseous chemicals, including AHF, HCl, H ₂O vapor, O₃ and N₂. During the in situ DI rinse, it is also possible to dispense AHF gas into the process chamber. It is believed that AHF will dissolve in the rinse water to form a dilute aqueous-HF solution (reactive rinse). In the epitaxial preclean work, three AHF-vapor cleaning processes were studied. In all three processes, the wafer was first exposed to a gaseous mixture of AHF, HCl, H₂ O and N₂. In the first AHF-vapor process, the vapor step was followed by a DI rinse and spin dry. In the second AHF-vapor process, the vapor step was followed by a reactive rinse and then a second DI rinse with no AHF gas and then a spin dry. In the third AHF-vapor process, the vapor step was followed only by the reactive rinse and a spin dry with no final DI rinse.

Fig. 2. Ex situ XPS surface analysis of fluorine and oxygen (atomic %) for various treatments of the silicon surface.7

To assess the benefits of integrated cleaning, analysis of the wafer surface and deposited films was carried out. The surface of single-crystal (100) silicon was analyzed by ex situ XPS following the three AHF-vapor cleaning processes and also following an aqueous-HF cleaning process. To perform the XPS analysis, all wafers were exposed to the atmosphere. Figure 2 shows the results of the XPS analysis. ⁷ An oxygen concentration of 1-3% (atomic percent) was detected with the conventional aqueous-HF process, while fluorine concentration was near the detection limit of 0.1%. The two AHF-vapor processes that ended with an in situ DI rinse had higher oxygen atomic concentrations at 7% and 4%, and also had higher fluorine concentrations at 0.7% and 0.3%. The AHF-vapor process that ended with the reactive rinse gave the lowest oxygen concentration at 0.8-1.9%, but gave the highest surface fluorine concentration at 1.4%.

Further understanding of the surface fluorine was gained by measuring the fluorine after a 6 Å ozone oxidation of the surface. ¹¹ During this slight oxidation, it appears that fluorine, which was previously buried, diffuses to the wafer surface, resulting in similar surface fluorine levels regardless of HF treatment conditions. It was concluded that when buried fluorine is taken into account, all the cleaning processes result in very similar near-surface fluorine content.

Profiling SIMS interface analysis after polysilicon and epi deposition on the wafer surfaces was also used to assess the benefits of integrated cleaning. In this case, the three AHF-vapor-treated wafers were transferred directly into the vacuum loadlock and were not exposed to the atmosphere before film deposition, while the aqueous-HF-treated wafer was necessarily exposed to the atmosphere.

Fig. 3. Profiling SIMS interface analysis of oxygen (% monolayer) after thin film deposition for various treatments of the silicon surface. 7

Figure 3 shows the results of the SIMS analysis.⁷ The oxygen trend was similar to that seen in XPS analysis; however, the AHF vapor process ending with the reactive rinse resulted in oxygen concentrations lower than the aqueous-HF process. This is clearly a result of the direct transfer of the cleaned wafer into the vacuum platform, thus avoiding atmospheric exposure. With epi deposition at 850°C, it can be seen that oxygen levels are below the detection limit for the integrated AHF-vapor, reactive- rinse process. It was also found that the higher fluorine concentration detected by XPS for the reactive- rinse process (Fig. 2) was reduced below the SIMS detection limit for the integrated epi deposition.⁶ It is believed that atmospheric exposure and oxidation will trap fluorine on the silicon surface.¹¹ This demonstrates a limitation of ex situ analysis of a cleaned silicon surface, which must be taken into account when trying to predict final interface concentrations of oxygen and fluorine.

Epi films grown under these conditions displayed superior properties when the integrated AHF-vapor, reactive-rinse cleaning process was used. However, it was found that a 950°C hydrogen pre-bake in the epi reactor was still required to achieve the best results.⁷

Integrated cleaning with the AHF- vapor process followed by a DI rinse and spin dry was also used for building the gate stack. ⁵ Good MOS devices were built, showing equivalent properties by GOI and IV tests with 65 Å oxide thickness at the 0.25 µm (250 nm) technology node. This indicates the feasibility of integrated gate stack pre-cleaning and shows promise for technology nodes beyond 0.25 µm.

Conclusion

In summary, integrated cleaning capabilities and benefits have been demonstrated on commercially available equipment and have been applied to the formation of low-temperature epi films and gate stack films. For low-temperature epi deposition, the influence of atmospheric exposure and the advantages of integrated cleaning are clearly shown. As device dimensions and gate oxides shrink, surface cleanliness will become even more critical, and integrated cleaning will become a necessity. The technology exists today to meet these challenges and ultimate implementation of integrated cleaning will depend on the movement toward single-wafer cluster processing.

References

1. Vermeulen, et al., "A HF vapor etch process for integration in cluster-tool processes: characteristics and applications," Cleaning Technology in Sem iconductor Device Manufacturing, ECS Proceedings, Vol. 94-7, 241(1994).

2. J. Ruzyllo, "Evaluating the feasibility of dry cleaning of silicon wafers," Microcontamination 6(3), 39 (1988).

3. Y. Ma, M.L. Green, "In situ vapor phase processes in an integrated cluster system for pre-gate oxide silicon surface cleaning," Cleaning Technology in Semiconductor Manufacturing , ECS Proceedings, Vol. 95-20, 115 (1996).

4. F. Glowaci, et al., "Integrated vapor phase cleaning and pure NO nitridation for gate stack formation," Rapid Thermal and Integrated Processing VI, MRS Symposium Proceedings Vol. 470, 229 (1997); B. Froeschle, et al., "Characterization of oxide etching and wafer cleaning using vapor-phase anhydrous HF and ozone," Rapid Thermal and Integrated Processing VI, MRS Symposium Proceedings, Vol. 470, 237 (1997).

5. D.C. Frystak, et al., "Gate stack formation using a fully integrated single wafer cluster tool," Rapid Thermal and Integrated Processing VI, MRS Symposium Proceedings, Vol. 470, 221 (1997).

6. R. Wise, et al., "Investigation of single-wafer, low temperature epitaxial silicon deposition with clustered HF pre-clean," Thirteenth International Conference on Chemical Vapor Deposition, ECS Proceedings, Vol. 96-5, 287 (1996).

7. D.C. Frystak, et al., "Surface preparation using anhydrous hydrogen fluoride and aqueous H₂O prior to low temperature epitaxial silicon deposition," Cleaning Technology in Semiconductor Manufacturing, ECS Proceedings, Vol. 97-35, 62 (1998).

8. R.A. Weimer, et al., "Method for forming hemispherical grained silicon," US Patent 5634974.

9. H. Gilboa, et al., "Integrated rapid thermal CVD processing solutions for 0.18-0.25 µm technologies,' Rapid Thermal and Integrated Processing VI, MRS Symposium Proceedings, Vol. 470, 215 (1997).

10. J.F. Weygand, et al., "Cleaning silicon wafers with an argon/nitrogen cryogenic aerosol process," Micro 15(4), 47(1997).

11. J. Barnett, et al., "Characterizing various process effects of an anhydrous HF system on surface and subsurface fluorine concentration," Proceedings of the Third International Symposium on Ultra Clean Processing of Silicon Surfaces, 265 (Acco, Leuven, 1996).

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