Options for CVD of Dielectrics Include Low-k Materials

		At a Glance
	Of the CVD methods for dielectric deposition, high-density plasma (HDP-CVD) and TEOS-ozone are the main methods for gap fill applications. Low-k options include fluorosilicate glass (FSG), fluoronated amorphous carbon (a -F:C) and parylenes. Some low-k options may only last one generation, so extendibility of a tool set may be essential.

A number of methods for depositing dielectric materials by chemical vapor deposition (CVD) are currently available. For current gap fill applications, CVD methods have their advantages. They are well-known processes, and they generally require a smaller number of overall steps than spin-on methods. For damascene processes, blanket deposition is all that is required for interlevel layers, and that can be done with either a CVD or a spin-on process. Pre-metal dielectric (PMD) and shallow-trench isolation (STI) will require effective gap fill capability whether damascene is used or not. For STI, high-aspect ratio (~4:1) trenches must be filled with high-quality dielectric material. 

The two main competitors for dielectric gap fill applications are high-density plasma CVD (HDP-CVD) and tetra-ethoxysilane (TEOS)-ozone. Both promise excellent gap fill performance well into the 0.13 µm (130 nm) generation. HDP-CVD films are said to be dry, compressive films that lend themselves well to multiple metal layer applications such as microprocessors. Since it is a plasma-based system, a typical HDP system would cost more than a TEOS-ozone system, but it provides the throughput advantages of requiring fewer process steps. TEOS-ozone is used in many DRAM applications, since the market is more cost sensitive, and TEOS-ozone equipment costs less. TEOS-ozone films, as others that depend on a flow mechanism, must be annealed, which adds steps and eats into thermal budgets.

Both methods can deposit a high-quality oxide, though each has its concerns. HDP-CVD is a newer technology that some think is more susceptible to metallic contamination, while TEOS-ozone can contain moisture. Effective chamber cleaning and avoidance of corner sputtering are the answers to HDP's concerns, while thorough anneals are the answer to the moisture problem.

Plasma-enhanced CVD (PECVD) oxide, where silane reacts with oxygen, is often used for cap and blanket layers. Most gap fill methods other than HDP-CVD and TEOS-ozone tend to use a flow mechanism similar to that in the TEOS-ozone method. Doped and fluorinated oxides can be deposited with or without plasma enhancement. CVD of parylene materials, like AF-4, is under investigation for low-k applications.

HDP-CVD oxide

Lead Photo: Two magnetically levitated turbomolecular pumps are required to remove process gases and byproducts from this 300 mm HDP-CVD process chamber. (Source: Novellus Systems)

The HDP-CVD oxide deposition process is actually a deposition-etchback process, where both are performed simultaneously. The plasma is a high-density mixture containing oxygen and argon. A dc bias pulls oxygen to the wafer surface where it reacts with silane (SiH₄) to form SiO₂. The argon simultaneously sputters deposited material away. The etchback is designed to remove overhang of the deposited material at the top of the gap. Although much of the deposited material is removed, it provides a time savings over some other methods since no anneal is required.

It was originally developed for intermetal dielectric (IMD) applications, but it also deposits high-quality material for STI, PMD and nitride etch-stop applications. Also, with the removal of the sputtering component of the plasma, it becomes a PECVD capping layer tool to prepare for chemical-mechanical polishing (CMP). However, it has been shown to be more cost-effective to use HDP-CVD just to the point of accomplishing gap fill and then use a separate PECVD chamber for the cap. ¹

HDP-CVD became production-worthy after vacuum pump throughput and wafer temperature concerns were addressed. High-speed turbopumps, with speeds up to 2000 liters/sec, were required to make HDP-CVD work for 200 mm wafers, and it is expected that speeds up to 5000 liters/sec will be required for 300 mm wafers. Conductance between the wafer and the pump is minimized in one case by putting the wafer directly over the throat of two high-throughput pumps (lead photo). In many cases, the wafer is biased with up to 3 kW of rf power, creating a tremendous heat load. Cooled electrostatic chucks, or chucks that have some other special design, are a part of the solution.

The etch:deposition (E:D) ratio, usually kept somewhere between 0.14 and 0.33, is controlled by the ratio of the gases, the chamber pressure, the ion-to-neutral flux ratio, the ion energy and the rf bias on the substrate. A low E:D ratio can lead to the formation of seams and knife-edge features, while a high E:D ratio can lead to corner erosion of the metal lines because of resputtering. This trade-off leads to questions about the ability of HDP-CVD to fill high-aspect ratio gaps in upcoming technology generations. The narrower gaps are more difficult to fill without eroding their corners.

Many believe that this problem can be worked around by varying the E:D ratio during deposition. Aki Sekiguchi, thin films process engineering manager at IBM (East Fishkill, N.J.), said, "If you don't do it carefully, you are going to sputter erode corners. There are ways to get around that. You can have multiple steps where you start off gently and then kick in the etching component. The concern is there, but you can work around it."

HDP-CVD is also a candidate for depositing fluorosilicate glass (FSG), a first-generation low-k dielectric. Silicon tetrafluoride (SiF₄ ) is used in place of silane. One potential problem for this material is that fluorine bonds are not always very stable, and free fluorine ions can attack just about anything. If fluorine ions encounter moisture, hydrofluoric (HF) acid is the result. One method for avoiding this problem is fluorine scavenging.² The introduction of hydrogen (H₂) during deposition can remove weakly bonded fluorine atoms.

The Ultima HDP-CVD Centura from Applied Materials (Santa Clara, Calif.) uses a tunable inductively coupled plasma (ICP) source and tunable gas distribution to provide ion density uniformity at the wafer surface. To combat impurity formation in deposited oxide, the chamber is made of all ceramic components, and a remote NF₃ plasma process is used to keep fluorine from attacking the chamber during cleaning. Its BLUE monopolar electrostatic chuck cools the center and edge of the wafer independently to provide temperature uniformity across the wafer.

Speed HDP modules from Novellus Systems (San Jose, Calif.) use a single ICP source with a continuous hemispherical ceramic dome designed to provide uniform ion density across the wafer. A bipolar electrostatic chuck is used for rapid chucking and dechucking and also to ensure uniform bias and temperature across the wafer.

The WJ200H and WJ3000H from Watkins-Johnson (San Jose, Calif.) feature an electrostatic shield for the rf source to reduce the average ion energy in the plasma. Lower ion energy is desirable to reduce particulates, contamination and device damage, and it is one of the controlling factors in the etch rate.

Fig. 1. The ATP system uses an inverted wafer, multichamber, rotary table design. (Source: Quester Technologies)

TEOS-ozone

The TEOS-ozone method works on the principle of a flowable chemistry. TEOS and intermediate molecules in their gas phase do not stick to the wafer surface well. This allows them to flow into trenches and gaps before adsorbing onto the surface and forming SiO₂. This is analogous to a liquid with a high surface mobility. This flowing property of the deposited material is the key to its ability to fill gaps and provide global planarity. The process has often been performed at reduced pressures to increase the mean free path, reduce particle generation and reduce background water vapor, though some believe there is no significant difference between subatmospheric CVD (SACVD) and atmospheric pressure CVD (APCVD).³

For STI and pre-metal applications, the fact that TEOS-ozone is not a plasma-based process can be an advantage. According to Dr. Maeda of Semiconductor Processing Laboratory (Shinagawa, Japan), "The corner damage introduced by high-density plasma is a concern together with the surface damage within the sensitive device gate area. On the contrary, for atmospheric pressure CVD ozone-TEOS, it is just a thermal CVD process." In addition to avoiding plasma damage concerns, the flow mechanism has its advantages. Maeda continued, "Flow-in CVD type step coverage is very good, even for sidewalls with a negative slope. If the gap has a negative slope, we can fill such gaps."

Quester Technology's (Fremont, Calif.) APT-5800 and 6000 Series equipment are TEOS-ozone systems that deposit doped and undoped layers using a low-temperature (400-500°C) atmospheric pressure process (Fig. 1). The ATP system architecture operates using an "inverted wafer," multichamber, rotary table design for optimized process condition control and throughput.

Mattson Technology (Fremont, Calif.) offers both silane and TEOS-based processes with its Aspen II CVD system. The Aspen system reacts liquid TEOS, rather than a TEOS vapor, with oxygen. The heated mixture is delivered to the wafer using a showerhead. Ozone is usually used to lower the temperature required to deposit an oxide film using TEOS. The Aspen II system processes four wafers at a time to allow a slower depostion rate without impacting throughput.

Concerns for the TEOS-ozone method are that the film absorbs water, and that an anneal is required to remove the moisture as well as densify the film. Residual water can cause problems in some applications, and depending on the wafer product, the anneal can gouge into the wafer's thermal budget. Doping uniformity is also a concern, since that can cause nonuniform removal rates with CMP; the polished surface can actually be wavier. For this reason, TEOS-ozone layers are usually capped with another layer that is more uniform, though some systems claim better doping uniformity than HDP-CVD systems. TEOS-based films containing fluorine for low-k applications are under development.

Table 1. Properties of Carbon-Based Materials4
Material	Composition	Structure	k	Thermal stability
Diamond or diamondlike carbon (DLC)	C	Crystalline, fully crosslinked	5.7	Very high
Hydrogenated carbon (a -H:C)	C&H,H: 30-50 at.%	Amorphous polymer, highly crosslinked	2.7-3.8	350-400°C
Fluorinated carbon (a -F:C)	C&F, F: 40-50 at.%	Amorphous polymer, highly crosslinked	2.1-2.8	300-420°C
PTFE or Teflon	C&F, F: 67 at.%	(-CF2 -) polymer, uncrosslinked	1.9-2.1	<300°C

Amorphous fluorinated carbon

Carbon compounds can have a dielectric constant as high as k = 5.7 for diamond or as low as 1.9 for PTFE (Teflon).⁴ A variety of these compounds is being examined for use as low-k dielectrics (Table 1). The form being developed for low-k CVD applications is amorphous fluorinated carbon (a -F:C). This material has k values low enough for the next one or two technology generations. It is typically deposited by CVD using C₄ F₈ and CH₄ as the reactants.

The main trade-off for the technology is thermal stability vs. dielectric constant. Highly crosslinked molecules have higher thermal stability. This can be accomplished either with a high wafer temperature or by adjusting the reactant ratio. The high temperature can reduce the amount of fluorine that stays in the material, which then increases the dielectric constant. That is in addition to the fact that the number of bonds available for fluorine atoms decreases as crosslinking increases.

Thermal stability is the key concern and the biggest challenge with very low-k dielectric materials. "Today's intefration schemes rely on multiple temperature cycles in the 400-430°C range. Most customers today are looking for film stability to 400°C to minimize issues with intefration," stated Dr. Dana Tribula of Applied Materials.

Fig. 2. HDP-CVD systems can provide a path through multiple generations of low-k dielectric materials. (Source: Applied Materials)

Amorphous carbon films can be deposited using HDP equipment (Fig. 2). "Right now, we have quite a few customers looking at FSG films as a first generation low-k material. For the longer term, our customers will be able to use the same tool set to deposit amorphous carbon, extending their equipment base through several device generations."

Other methods

The Flowfill and Low-k Flowfill methods developed by Trikon Technologies (Newport, Gwent, UK) take advantage of a liquid state dielectric to flow into gaps to fill them. For the Flowfill method, silane is reacted with hydrogen peroxide (SiH₄ + H₂O₂). Monosilicic acid (Si(OH)₄) condenses on the wafer surface in a liquid form. The wafer is held at a temperature of about 0°C, so that the monosilicic acid flows without polymerizing. For the Low-k Flowfill method, methylsilane (CH₃SiH₃) is used instead of silane. Base and cap layers are required, as well as an anneal to remove water.

A number of polymer materials are being studied for IMD applications ( see "Dielectric Anisotropy in CVD Polymer Thin Films"). The material that has gained the most attention is a parylene called AF-4 (Fig. 3).^5,6 According to T.S. Ravi of Novellus Systems, "With a k of 2.2 to 2.3, AF-4 has attracted a lot of attention as the next-generation, low-k CVD film. It deposits as a conformal film and is the only low-k polymer that is stable up to 450°C. We are working with several customers to integrate it as an intermetal dielectric both in the subtractive metal and the copper damascene approach."

One of the applications studied for AF-4 is an embedded dielectric. AF-4 is used to fill between closely spaced metal lines, where its low-k value would have the most beneficial effect on RC delays. ⁵ Oxide would then be deposited on top of these filled structures to provide a mechanically stable interlevel layer, for which there is a well-understood via creation and filling technology. Vapor deposition of parylene materials is a well-established technology, but mechanical strength and applicability to via and damascene processes are still under investigation.

Fig. 3. AF-4 is the parylene material receiving the most scrutiny as a low-k dielectric.

Conclusion

The HDP-CVD method is gaining popularity for depositing dielectric materials because of its ability to deposit dry compressive films, fill gaps, forgo annealing and reduce the overall number of process steps, while TEOS-based systems will continue to hold their ground in more cost-sensitive markets. Both methods claim the ability to service the needs of technologies down to the 0.13 µm level.

Many have chosen to pass over either HDP-CVD or TEOS-ozone. Some chose to go from spin-on glass to HDP-CVD, passing over TEOS-ozone. Others have chosen to forgo HDP-CVD to go from TEOS-ozone to future solutions such as parylenes.

CVD methods for depositing low-k dielectrics will start with fluorinated oxides. Fluorinated amorphous carbon will be ready to step in as a second generation low-k material, though other materials may also be ready by then.

References

1. D.S. Armbrust, A.K. Stamper, L.A. Serianni, M.A. Trahan "Integration of HDPCVD FSG for 0.25 µm CMOS Technology," DUMIC, 1998.

2. L.Q. Qian, H.W. Fry, G. Nobinger, J.T. Pye, M.C. Schmidt, J. Casillas, M. Lieberman, "High Density Plasma Deposition and Deep Submicron Gap Fill with Low Dielectric Constant SiOF Films," DUMIC, 1995.

3. G. Cogin Schwartz, K.V. Srikrishnan, "Interlevel Dielectrics," Handbook of Semiconductor Interconnection Technology, Marcel Dekker, 1998.

4. H. Yang, T. Nguyen, Y. Ma, S.-T. Hsu "Significant Improvement of Thermal Stability on Low-k Fluorinated Amorphous Carbon: Two Approaches," DUMIC, 1998.

5. J. Gaynor, A. Ralston, "AF4 as a VLSI Interconnect Material," Semiconductor International, December 1997.

6. J. Wary, R. Olson, W. Beach, "Polymer Developed to be Interlayer Dielectric," Semiconductor International, June 1996.