Backside Emission Microscopy Pinpoints Wafer Level Defects

		At a Glance
	Backside thinning and reinforcement of wafers, combined with ultralow-force probe needles, make it possible to locate chip-level defects even for devices where the frontside is inaccessible.

Emission microscopy to locate chip-level defects has been a routine form of analysis for more than a decade. The majority of both static and dynamic defects emit light, and emission microscopes capture and intensify this light to pinpoint the defect's location. A complete emission image consists of the light emitted by the defect, superimposed on an illuminated image showing the circuitry of the device. As the number of elements on a chip has risen, the ability to pinpoint a defect that may be confined to a single transistor has become more significant.

Generally, light emissions from packaged devices and wafers have been collected from the frontside because defects have typically emitted light upward from the die's active face. Defects under metalization emit light at an oblique angle, which has led to the development of wide-angle, low-magnification lenses to perform the initial capture. The number of metalization layers is critical: Defect emissions can escape upward from beneath two or three layers, but not more. As design rules shrink, the number of layers of metalization required increases, preventing defect emissions from reaching the frontside.

In late 1996, technology was introduced to thin the backside of packaged devices. Since defects emit light isotropically, the new technology -- which removes both backside packaging and a calculated thickness of backside silicon -- permits engineers to collect defective emissions from the backside of packaged devices (lead photo).

Backside imaging and defect detection

Thinning of wafers, however, was more difficult. Many failure analysts used the approach of lapping a wafer's entire backside area. While this method permitted emissions to escape, it also resulted in a wafer that was so thin it could not be handled or probed without breaking. Finding defect emissions at the wafer level remained important, partly because it is economically advantageous to locate defects as early as possible.

Emission micrograph from the backside of a wafer showing a typical backside image at 20X (300X magnification). There is evidence of leakage.

Recent advances in semiconductor technology have considerably increased the desirability of backside wafer imaging. The number of layers of metalization is increasing in some microprocessors and logic devices. Currently, such devices have three to seven layers; by late 1998, design rules will shrink from 0.35 µm (350 nm) to 0.18 µm (180 nm), and the number of layers will grow accordingly (Fig. 1). If light emissions from defects are to be collected, they must be collected from the backside.

A different problem, but with the same result, has evolved in lead-on-chip (LOC) DRAMS. Since the bond pads are lined up across the device's center, probe needles reaching to the bond pads block light emitted by defects when the device is biased. LOC DRAMS must also be imaged from the backside. In both instances, it is desirable to locate defects at the wafer level. The defects can have numerous causes but are most often associated with leakage. Once an emission microscope has pinpointed the location, the cause of the defect can be analyzed with a scanning electron microscope (SEM). However, yield development engineers must have a practical means of collecting light emissions from the backside of the wafer in order to give coordinates to the SEM. Shown in Figure 2 is a diagrammatic side view showing a short wafer segment. An individual device has been backside-thinned and reinforced. The wafer is mounted face down on an emission microscope. An ultralow-force (ULF) probe card is applied to active die face (bottom); the emission microscope lens collects light emitted upward through the remaining silicon by static (leakage) and dynamic (functional) defects at chip level. The same fixturing is used with illumination from above to make a reference image of the circuit structure. An overlay of emission image and reference image forms the final image, showing defect locations.

Fig. 1. Impact of metal conducting material selection as design rules shrink.

Fig. 2. A diagrammatic side view showing a short wafer segment.

A basic problem in backside emission collection is the silicon filter effect. The frequencies emitted by defects are to some degree absorbed by the silicon they pass through. Emissions around the silicon bandgap at 1070 nm suffer the least absorption. Heavily doped silicon is considerably less transparent to emissions than lightly doped silicon. If a wafer is left at its full thickness -- 640 µm, for example -- few emissions escape to the backside. The thickness of silicon that an emission will pass through varies. Generally, P(-) silicon must be thinned to 200-250 µm and P(+) silicon to between 80-120 µm to permit backside imaging. The object is to thin the silicon sufficiently so that the escaping emission is strong enough to allow detection using currently available CCDs, which have a quantum efficiency of up to 80%. If the fraction of light escaping is as low as 0.1%, an emission image can be made. The fraction can be as low as 0.01%; below this level, successful emission imaging is generally impossible. New HgCdTe arrays, now being developed, will permit even greater sensitivity.

The second significant obstacle in backside imaging of wafers is the fragility of the wafer itself. In normal probing, the wafer is supported on the backside by a metal chuck; in emission microscope work, the wafer is mounted face down. Probe needles reach the wafer from below, while the microscope's lens is positioned above the wafer. There is no metal chuck or other support for the wafer. If 100 or more needles are used, the mechanical force of normal probe needles is sufficient to break even an unthinned wafer (Fig. 3).

Fig. 3. A typical configuration for backside inspection shown without the emission microscope optics or sensor. Note the double platen and secondary CCD for positioning microprobes or a probe card.

Fig. 4. A complete backside emission microscopy probing system with a ULF probe card. Note the probe pins point up. A locally thinned wafer (not shown here) will be placed between the probe card and the optics assembly, with the backside facing upward.

The concept of working with wafers from the backside originated at Karl Suss (Dresden, Germany). Recognizing that backside access to wafers would soon become a necessity, Karl Suss designed and built the first wafer-level backside probe stations (Fig. 4). The way was thus open for the technology of emission microscopy to develop backside emission-collection tools.

The fragile wafer

Automated backside thinning of selected individual die on wafers or packaged devices was introduced in 1996, when increasing layers of metalization first made frontside imaging impossible for some devices. To thin a single die, the instrumentation was required to remove backside silicon (and packaging material, if present) to an adequate depth without damaging the leads. The area from which silicon was removed had to correspond precisely in its X and Y dimensions to the die's active area. It was also necessary to avoid outright breakage of the silicon, although this problem is much less severe for packaged devices than it is for wafers. During development of the backside thinning system, much was learned about the transmission of light from various types of defects through silicon of various thicknesses and with different types of doping.

After thinning of a packaged device, the silicon remaining at the bottom of the cut may be only 80-200 µm thick, but it is reinforced by the remaining packaging material. When an individual die is backthinned on a wafer, the cut is surrounded only by full-thickness silicon. While reducing the silicon to a 200 µm thickness is sufficient to permit the escape of defect emissions in many devices, some devices using heavily doped silicon require thinning to as little as 80 µm.

In thinning individual die on a wafer, it was found that reinforcement by bonding a glass or quartz insert to the cut's bottom increases the wafer's stiffness. This is sufficient to permit handling and, in particular, to permit frontside probing of the thinned die. As an additional benefit, the insert enhances the optical properties of imaging in several ways.

To understand the relationship between the mechanical load imposed by probe needles and the stress release behavior of silicon, extensive testing was carried out with wafers thinned to half thickness (320 µm). To simulate the backside cut required for emission collection, a circular hole 24 mm in diameter was cut in each wafer's center. A point load was then applied, and the wafer's deflection was measured.

When the load reached about 900 grams, 150 mm wafers broke. While these results were not unexpected, they made it clear that it would be difficult to use ordinary probe cards on wafers where the chuck support has been removed to permit backside emission collection. It is usually desirable to use a fairly large number of needles -- from around 30 to around 100 -- to obtain adequate data and to prevent individual I/O from floating high or low.

A single, conventional tungsten probe needle places a 10-16 gram load on the wafer. When 100 needles are used, the load is between 1.0-1.6 kg, well above the 900 gram load at which even a full-thickness wafer breaks.

Fig. 5. ULF probe card assembly for backside inspection of wafers. The probe card generates only 1.2-1.5 grams of force per needle vs. 10-16 grams for conventional tungsten probe needles.

Solving the load problem

The solution was to develop new probe cards with needles that place a much smaller load on the wafer. By greatly increasing each needle's conductivity, the load per needle was reduced to 1.2-1.5 grams. If 100 ULF needles are applied, the total load is 120-150 grams, well below the breakage load even for a wafer where the entire area has been thinned (Fig. 5). This load is also well within the limits for a single insert-reinforced die where the silicon has been thinned to as little as 80 µm. As a result, backside emission microscopy can be carried out on wafers for both static and dynamic defects.

The two innovations described, backside thinning/reinforcement of wafers and the use of ULF probe needles, permit the localization of chip-level defects even for devices where the frontside is inaccessible. Backside emission of wafers can be carried out both for static defects (forward-biased emissions, avalanche, hot electron effects and saturated device emissions) and for dynamic functional defects. For functional defects, test vectors are input from ATE equipment while the wafer is mounted on the emission microscope. Numerous individual die can be thinned and imaged on the same wafer.