Tantalum, Copper and Damascene: The Future of Interconnects

		At a Glance
	The industry appears ready to quickly move to an entirely new interconnect strategy that employs tantalum diffusion barriers and copper interconnects, formed by a dual damascene patterning process. The copper interconnects will be formed with a two-step process, involving a PVD or CVD copper seed layer, followed by electroplating.

C opper is poised to take over as the main on-chip conductor for all types of integrated circuits (ICs). Compared to aluminum, which is now used almost exclusively as the main interconnect material, copper has a lower resistance(<2 µV-cm even when deposited in narrow trenches vs. >3 µV-cm for aluminum alloys). This lower resistance is critically important in high-performance microprocessors and fast static RAMs, since it enables signals to move faster by reducing the so-called RC (resistance x capacitance) time delay. The first implementations of copper interconnects will almost certainly be for those types of high end applications. 'To hit the performance that we need in most of our very high performance parts like microcontrollers, microprocessors and fast static memories, we really need to have copper in there,' said Fabio Pintchovski, director of Motorola's Advanced Product Research and Development Lab (APRDL, Austin, Texas).

But the advantages of copper are so strong that many see it being adopted for most, if not all, types of ICs, not just for high-performance parts. For example, copper enables a reduction in not only the resistance part of the RC equation, but the capacitance part as well, since the metal lines can be made thinner. This helps reduce the amount of power consumption, which makes it attractive for use in battery-powered applications, such as notebook computers. 'Even if the amount of current going in is about the same as before, the power consumption goes down simply because the copper lines are significantly thinner,' explained Ashok Sinha, president of the metal deposition group at Applied Materials (Santa Clara, Calif.). 'As the films get thinner, the capacitance on the chip -- which is primarily sidewall capacitance between the adjacent lines of copper -- is less. If you combine thin copper lines with a moderately low-k dielectric, the chips consume significantly less power.'

Another major benefit of copper is that it has superior resistance to electromigration, a common reliability problem in aluminum lines. This means that copper can handle higher power densities, such as those found in high-power transistors, which broadens its application to a whole new range of analog devices.

A third -- and some say most important -- benefit of copper is that it can actually lead to lower manufacturing costs compared to aluminum. This can come about in one of two ways. First, because copper is difficult to etch, a new strategy called 'damascene' or 'in-laid' patterning was developed to form the interconnect lines (Fig. 1). IBM, which pioneered the process, now reports that the damascene approach requires 20-30% fewer steps than traditional subtractive patterning. 'Coupled with the use of copper for reasons of speed and reliability performance factors is a potential reduction in manufacturing costs as the dual damascene architecture is implemented in place of the subtractive aluminum with via fill,' noted Elliot Broadbent, chief scientist at Novellus (San Jose, Calif.). Not only are there fewer steps, but dual damascene eliminates or reduces the need for some of the most difficult ones, including the aluminum etch and many of the tungsten and dielectric CMP steps. 'Many of the processes that are yield limiting or costly are now reduced because you've made the jump to the new material,' added Alain Harrus, chief technology officer at Novellus.

A wafer deposited with copper is moved between chambers on a to-be-introduced deposition system from Novellus.

The second way copper can reduce costs is that because smaller lines can be used to carry the same amount of current, a tighter packing density can be achieved per level. This means that fewer levels of metal are needed, leading to significantly reduced manufacturing costs (Fig. 2). 'One of the main motivations for using copper is that for certain devices, you need only about half of the metal layers with copper than you would have to use with aluminum and tungsten,' Broadbent said. Copper proponents believe that for these reasons, even cost-sensitive DRAM manufacturers will soon move to copper, perhaps for the 1Gb generation.

Fig. 1. The first implementations of copper will be achieved with dual damascene architecture, PVD-deposited tantalum-based diffusion barriers and copper seed layers, and electroplated copper fill.

Fig. 2. One of the main benefits of copper, beyond the ability to increase chip speed and reduce power consumption, is that the number of metal levels can potentially be reduced by as much as half. (Source: M. Bohr, Intel)

As part of its 'CMOS 7S' technology, IBM will soon put copper interconnects into production for its ASIC line of products.

A fourth, less tangible benefit of copper is its market appeal. Companies that adopt copper early are sure to win favor from stockholders and investors (certainly, the difference between copper and aluminum is something even the most nontechnical can grasp). For this reason, as well as the very real benefits of copper, it is likely that we will soon see IC foundries hopping on the copper bandwagon. Indeed, most of the large foundries are said to already have copper development programs in place.

Why the industry has not shifted to copper until now is due to several reasons. One is that there is a natural reluctance to introduce new materials into manufacturing, as there are always some unforeseen problems that arise. Another is that copper is a known fast-diffuser and can act to 'poison' a device, creating a failure, once it gets into the active area (i.e., source/drain/gate region of the transistor). This has required the development of new and advanced diffusion barriers to eliminate that threat, as well as different fab layouts to isolate the copper production part of the line from the rest of manufacturing. A third reason is that copper patterning requires the implementation of an entirely new manufacturing technique (i.e., damascene). 'The damascene process takes a while to learn,' cautioned Motorola's Pintchovski. 'If you haven't started yet, you have a long way to go.'

So, despite the many advantages of copper, many believed that the industry's lack of experience (and limited availability of copper-oriented production equipment) would probably delay the introduction of copper until after the year 2000. This is not so: Late last year, IBM, quickly followed by Motorola and Texas Instruments (TI, Dallas, Texas), announced aggressive plans to put copper into production in 1998.¹ Perhaps even more surprising was the news that the bulk of the copper would not be deposited by conventional methods (such as PVD or CVD), but by electroplating -- the same technology use to plate chrome onto bumpers and copper onto printed circuit boards.

At the same time, it became apparent that the industry was planning to delay the introduction of materials with low dielectric constants (low-k dielectrics), which actually have a much greater potential to reduce RC time delays.² 'Much attention has been paid recently to the use of copper wires in integrated circuits,' said Robert Havemann, manager of advanced interconnect development at TI. 'While lowering resistance with copper solves a near-term problem, we think reducing the capacitance effect is even more of a critical issue, because unless that problem is solved, chip performance, power and operating voltage will ultimately be limited by the interconnect. That's counter to everything the market expects from future semiconductor products.'

Although TI recently demonstrated a successful integration of a low-k dielectric and copper ( see SI, May 98), it appears as if the first generation of copper that goes into production will be integrated with standard SiO₂ . In part, this is because a clear low-k winner has yet to emerge from a variety of low-k candidates under evaluation, but it is mainly because there are enough risks in trying to implement copper, let alone copper and low k. On the other hand, industry watchers believe that a fluorinated oxide with a moderately low k of 3.5 could be used with copper.

How they plan to do it

The details of how IBM, Motorola and TI plan to implement a copper interconnect strategy were announced in December 1997 at the International Electron Devices Meeting (IEDM) in Washington, D.C.

From these papers, and through interviews with industry sources, we believe we can paint for you a fairly accurate picture of the manufacturing processes that will be used for the initial implementation of copper. Here is how it will look:

Fundamentals of Copper Electroplating Jonathan D. Reid, Novellus Systems Electrodeposition of metal is performed by immersing a conductive surface in a solution containing ions of the metal to be deposited. The surface is electrically connected to an external power supply, and current is passed through the surface into the solution. This causes reaction of the metal ions (Mz-) with electrons (e-) to form metal (M): Mz- + ze- = M(O). In the case of electrodeposition of copper onto a silicon wafer, the wafer is typically coated with a thin conductive layer of copper (seed layer) and immersed in a solution containing cupric ions. Electrical contact is made to the seed layer, and current is passed such that the reaction Cu2+ + 2e- Cu(O) occurs at the wafer surface. The wafer, electrically connected so that metal ions are reduced to metal atoms, is referred to as the cathode. Another electrically active surface, known as the anode, is present in the conductive solution to complete the electrical circuit. At the anode, an oxidation reaction occurs that balances the current flow at the cathode, thus maintaining electrical neutrality in the solution. In the case of copper plating, all cupric ions removed from solution at the wafer cathode are replaced by dissolution from a solid copper anode. In the absence of any secondary reaction, the current delivered to a conductive surface during electroplating is directly proportional to the quantity of metal deposited (Faraday's law of electrolysis). Using this relationship, the mass deposited can be readily controlled through variations of plating current and time. With no applied potential or current flow across the interface between a metal and a solution, an equilibrium potential exists between the two. Once potential is shifted by an external power source away from the equilibrium potential, a current will be driven across the interface. Under conditions typical of most plating processes, this current flow is approximated by an exponential relationship known as the Tafel equation. The figure shows a current-potential curve typical of a copper deposition process. As potential is scanned from the equilibrium potential to more negative values, the current increases in an exponential manner (Tafel region) where the overall deposition rate is determined largely by charge transfer or reaction rate kinetics at the cathode. This strong dependence of current upon potential results in the need for plating cell designs that yield uniform potentials across the wafer surface. As potential continues to increase, mass transfer effects become predominant, and a limiting current plateau is reached. This results as the species reacting at the cathode (Cu2+) no longer reach the interface at a rate sufficient to sustain the high rate of reaction. As a general rule, plating processes are operated at currents no greater than 30-50% of the limiting current in order to avoid undesirable deposit (film) characteristics. To ensure that the rate of mass transfer of electroactive species to the interface is large compared to the reaction rate and uniform across the wafer surface, the rates of migration, diffusion and convection must be understood and controlled. Convection is the most important mode of mass transfer and can vary from stagnant to laminar or turbulent flow. It includes impinging flow caused by solution pumping, flows that are due to substrate movement and flows resulting from density variations. Electroplating can be carried out using a constant current, a constant voltage, or variable waveforms of current or voltage. Using a constant current, accurate control of the mass of deposited metal is most easily obtained. Plating at a constant voltage and using variable waveforms requires more complex equipment and control but can be useful in tailoring specific thickness distributions and film properties. A current-potential curve typical of a copper electroplating process.

• Tungsten plugs will be used at the first level of metal to contact the source, drain and gate regions, because of concerns over copper poisoning. In some cases, this tungsten may be patterned for short wiring runs. The rest of the metal, including vias, will all be made of copper.
• The copper will be patterned with a dual damascene strategy that employs a silicon-nitride etch stop/hard mask. Here, for a self-aligned via scheme, the nitride (or a film of the nitride 'family') will be deposited on top of a blanket layer of SiO ₂ and patterned -- this will later be used to form the vias. Next, a second layer of SiO₂ is deposited on top of the patterned nitride. This is also patterned and etched to form the trenches in the top layer of oxide. This etch stops on the silicon nitride, except where the mask has been removed. In these regions, the etch continues on to form the vias.
• Diffusion barriers will be tantalum-based, consisting of either elemental tantalum, tantalum with light amounts of nitrogen doping or a full tantalum nitride compound. These will be deposited by ionized physical vapor deposition (PVD). The pre-clean step here may prove critical.
• A copper seed layer will be deposited on top of the diffusion barrier as a prerequisite for the subsequent electroplating operation. This will be done with PVD (probably ionized PVD) for at least the first generation, and perhaps by CVD for the second generation because of CVD's superior step coverage. For the electroplating process to be successful, it is critical that this seed layer be continuous and free of pinholes (Fig. 3).
• The via and trench will be filled with copper by electroplating (also called electrochemical deposition).
• The copper will be planarized with a chemical-mechanical polishing (CMP) step. The main challenge here is to obtain the same polishing rate on the tantalum, which is a hard refractory metal, and the copper, which is comparatively soft.
• A silicon nitride layer will cap off the copper, keeping it totally encapsulated (silicon nitride on top, tantalum-based diffusion barriers on the sides and bottom).

'We have progressed very far to the point where we have produced actual parts that will be put into manufacturing at the end of the year, and successfully so,' Pintchovski said. He said the first devices to be manufactured with copper will be microprocessors and fast static RAMs. 'These will be followed pretty closely by DSP type parts, and then we'll extend to the rest,' he said.

Fun with electroplating

Electroplating is relatively simple, at least compared to aluminum deposition. It does not require ultrahigh vacuum, nor does it require complex heating. As explained in the sidebar 'Fundamentals of Copper Electroplating,' the wafer is connected to the cathode and immersed in a solution containing cupric ions and, of course, the anode. The amount of copper deposited is dependent on the current delivered. As with other types of deposition, the success of the process is measured by factors such as film morphology, step coverage, filling capability, uniformity across the wafer and from wafer to wafer, deposition rate, etc.

In practice, the process is fairly complicated, especially when you consider the aspect ratios and geometries of the holes being filled. According to Tom Taylor, global product marketing manager of the metalization group at Semitool (Kalispell, Mont.), the two key aspects of the electroplating process are the contents of the electroplating solution and the way in which the current is applied. One solution recently reported includes CuSo₄, HCHO, a surfactant and KCN. 'Something that's not often appreciated is that the electrolytes that are employed -- we refer to them as copper sulfate, sulfuric acid and water -- are actually more complex than that.' For example, Taylor said surfactants do not actually work as wetting agents, but really act to modify the way in which copper deposits on the wafer. This can be useful in that there are differences in the current density at the top of a damascene trench as opposed to that on the sidewall and at the bottom of the via. 'In an unmodified electrolyte, the plating rate is a direct function of current density,' explained Taylor. 'If you have a high current density at the top of a structure and a lower density at the bottom, you get a differential plating rate. If it plates faster at the top than it does at the bottom, you can pinch it off.'

One way around that is to apply a waveform to the cathode/anode system so that it is virtually like the dep/etch sequence that the high-density systems employ. 'By judicious selection of an oscillating electric field between cathodic and anodic potential, and the amplitudes that are applied, you can produce a dep/etch sequence that polishes copper from the high-density regions more quickly than it does in the low-density regions, and produce the required gap fill capability in that way,' Taylor said.

Another method is to include organic additives, of which surfactants are one class. 'If the additives adsorb or desorb in a way that offsets the current density distribution, you can modify or suppress the plating rate in a high current density region as compared to a low current density region. This in effect is called leveling,' Taylor said.

According to Chiu Ting, president of recent start-up CuTek, electroplating with organic addivitives, such as brighteners and levelers, leads to enhanced Cu deposition at the bottom of trenches. Brighteners produce fine deposits by masking the preferential growth sites/planes. Levelers enable the deposition of thicker films in small recesses and thinner films on small protrusions, relatively speaking. Ting said establishing the proper agents with the specific action and proper concentration ratio of leveler to brightener 'often determines the success or failure of a given gap filling plating process.'

Of course, an electroplating process must also address a variety of other issues. Because of concerns of copper contamination, it is critical that no copper be deposited on the backside of the wafer, for example. Perhaps the greatest challenge is one that is out of the electroplater's control: If the seed layer is not perfect (i.e., continuous), it can create a void in the copper fill.

Presently, Semitool offers a production tool called the LT-210, the first of which shipped late last year. The company also offers an R&D system called the Equinox.

An electroplating system is also being developed by CuTek, founded by Ting, who worked at AMD (Sunnyvale, Calif.) to develop an impressive electroplating process, coincidentally with a Semitool system (see SI , August 1997, p. 40 print edition). According to Ting, the CuTek process has been demonstrated, and the company is now working on automated wafer and handling and wafer control capabilities. 'Hopefully, in a few months, if we put them together and don't encounter too much trouble, we can ship a system by the middle of next year.'

Electroplating systems are also under development at Applied Materials and Novellus. Neither company has released any details on their respective systems, although Applied has said it expects to formally introduce the system by the end of the year.

In the meantime, Applied Materials has introduced the Endura Electra Cu system, which integrates a pre-clean, PVD Ta/TaN and PVD Cu process all on one Endura platform.

Novellus, through last year's acquisition of Varian's Thin Film Process Division, announced a new ionized PVD process called HCM (Hollow Cathode Magnetron) and is close to announcing a tool that integrates the deposition of tanatlum-based diffusion barriers by PVD and a copper seed layer, also by PVD.

Of course, most, if not all, suppliers of PVD equipment are also working to develop solutions for depositing tantalum barriers and copper seed layers. CVC (Rochester, N.Y.), for example, offers copper capabilities (including MOCVD) on its new Connexion 800 system. Sputtered Films (Santa Barbara, Calif.) has done a significant amount of work in the copper field, including analysis of various binary and tertiary diffusion barriers. Another company to watch is Genus, which has developed a tungsten nitride diffusion barrier, which could prove to be a viable alternative to tantalum-based barriers.

Conclusion

By the second half of this year, at least one company will have copper in production for microprocessors and for fast static memories. Next year, the use of copper will be fairly widespread.

References

1. P. Singer, 'Copper Goes Mainstream: Low k to Follow,' Semiconductor International, Nov. 1997, p. 67.

2. P. Singer, 'Chasing the Promise of Faster Chips,' Semiconductor International, Nov. 1996.

3. P. Singer, 'Making the Move the Dual Damascene Processing,' Semiconductor International, August 1997, p. 79.

Copper CMP Challenges Rajeev Bajaj, CMP Process Development Manager, Lam Research Corp. Planarizing copper is no less challenging than depositing copper for damascene interconnect structures. Copper chemical-mechanical planarization (CMP) for damascene structures involves developing a polish process that minimizes the pattern density and feature size effects associated with typical CMP processes. Development is complicated by new barrier materials, the lack of commercial slurries and the material properties of copper itself. Another significant challenge for CMP system manufacturers is the parallel development of copper, barrier and dielectric deposition processes. Process considerations With conventional processing technology, planarizing interlevel dielectric (ILD) polish occurs after every metal deposition and etch step. The same is not true for damascene processing, wherein the post-polish surface is expected to be free of topography. However, topography is induced because of erosion of densely packed small feature arrays and dishing of the metal surface in large features. These problems are commonly controlled by a compensation strategy using metal fills and dummy structures -- a costly solution in terms of lost silicon for ICs and added process and design complexity. It would be ideal to polish inlaid structures without the aid of such process and design steps. Copper CMP is more complex because of the need to remove the tantalum or tantalum nitride barrier layers and copper uniformly without overpolishing any features. This is difficult because current copper deposition processes are not as uniform as the oxide deposition process. Finally, tolerances for erosion and dishing are much narrower for copper CMP. Working with copper Copper has properties that add to the polish difficulties. Unlike tungsten, it is a soft metal and subject to scratching and embedded particles during polishing. Also, because copper is highly electrochemically active and does not form a natural protective oxide, it corrodes easily. Therefore, protecting the copper surface during polish, clean and subsequent processing will be essential. Equipment and materials suppliers face many challenges in providing solutions for copper interconnect CMP. Future challenges include the continued shrinking of feature sizes and increased pattern density variations, needing more aggressive dishing and erosion requirements. The introduction of new low-k dielectrics, such as fluorinated oxides followed by fluoropolymers, will continue to provide challenges for CMP and PCMP processes. Copper was polished over dense arrays ( top) and wide features ( bottom) using linear planarization technology, a new technology under development at Lam Research Corp. Remaining copper thickness over each area was nearly equal at about 6200 Å.