Using Flex for CSPs
CSPs leverage surface mount technology, and wafer thinning technology advances
Staff -- Semiconductor International, 6/1/1998
Using Flex for CSPs
A wide variety of methods for making chip scale packages (CSPs) that use organic and flex substrates were presented at the 1998 International Conference on Multichip Modules and High Density Packaging in Denver, Colo., in April. One of them was the multi chip scale package (MCSP), presented by Hightec MC AG (Lenzburg, Switzerland). It uses a multilayer flex substrate to build a 3-D multichip package with an outline the size of a die.
Chips are flip-chip attached onto the flex substrate, which is supported by a piece of glass, along with solder bumps for package I/O (see figure). After the chips are underfilled, the flex film is removed from the supporting glass. The film is then folded, and adhesive is applied at the necessary points to keep the module together.
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Fig. 1. MCSPs use a flex substrate to perform chip stacking. |
Both packages use a maskless meniscus bumping technique to bump the chips. An electroless Ni deposition of about 15 µm is followed by an Au/Sn solder deposition, also about 15 µm thick. Flip-chip attach to a flex interposer is performed using a fiber push connect technology. A modified wirebond head holds an optical fiber, which holds the flex substrate against the bump. Laser pulses are delivered to the solder ball through the fiber. IR emission from the solder goes back through the fiber to a detector for temperature monitoring.
Plasma Wafer Thinning
Tru-Si Technologies (Sunnyvale, Calif.) has developed a wafer thinning technology that can reduce the thickness of a silicon die to the 4-10 mil (100-250 µm) range for use in ultrathin packages. The Tru-Etch 2000 system uses the company's atmospheric downstream plasma (ADP) etching and wafer handling technologies to achieve those thicknesses.
Existing wafer grinding processes can achieve thicknesses of 10-14 mils (250-350 µm), and they are subject to post grind stress and damage. The ADP process is said to have no stress or damage problems, and to have an ability to thin to less than 4 mils with very high uniformity.
Current wafer etching and polishing processes, such as wet etch and chemical-mechanical polishing (CMP), use hazardous chemicals and large amounts of deionized water. ADP is a dry etch method designed to address those issues. Since it is a downstream process, there is no danger of plasma ion induced damage, and the company claims that frontside protection is not necessary. Also, since it is an atmospheric pressure process, there are no vacuum steps to reduce throughput.
The process is said to be a highly repeatable and reproducible isotropic etch process that removes a uniform layer of silicon from the wafer. It also has high etch rates for common materials present on the backside of processed wafers, including silicon, silicon oxide, silicon nitride, polysilicon and BPSG.
The company has also developed a wafer handling system to ensure protection
of the frontside and edge of the wafer from damage during processing.
Focused Technology selected Kulicke & Soffa (Willow Grove, Pa.) to provide front-of-line (FOL) assembly equipment for its first factory in Hsin Chu, Taiwan. The facility is scheduled to be operational by mid-1998, to assemble and test QFP and TQFP devices.
ADFlex Solutions Inc. deployed advanced flip-chip volume assembly capability to operations in its Lamphun, Thailand, facility, in addition to the surface mount technology (SMT) and chip-on-flex (COF) assembly already in place.
Sheldahl (Northfield, Minn.) received multiple production orders from Texas Instruments (TI, Dallas, Texas), for ViaThin high-density tape ball-grid array (TBGA) packages.
ChipPAC recently announced that its µBGA line is open and in full ramp at its Ichon, Korea, facility. The company expects to add three more µBGA modules there by the end of the year. The company also announced the completion of its 5000 ft 2 Technology Development Center in Chandler, Ariz.
MRS Technology (Chelmsford, Mass.) plans to use its technology for flat panel displays (FPDs) and other large-area electronic devices (LAEDs) to enter the market for high-density interconnect (HDI) with high-density single- and multichip packaging. The company also reported having received an order for a customized Model 5200 PanelPrinter from a U.S. manufacturer of HDI solutions.
The Panda Project (Boca Raton, Fla.) received pre-production qualification orders for its VSPA package from Tandem Computers (Cupertino, Calif.), SAAB Dynamics AB (Linköping, Sweden) and EG&G IC Sensors (Milpitas, Calif.). Tandem Computers also made a similar order for Compass Connectors.
Using Flex for CSPsA wide variety of methods for making chip scale packages (CSPs) that use organic and flex substrates were presented at the 1998 International Conference on Multichip Modules and High Density Packaging in Denver, Colo., in April. One of them was the multi chip scale package (MCSP), presented by Hightec MC AG (Lenzburg, Switzerland). It uses a multilayer flex substrate to build a 3-D multichip package with an outline the size of a die.
Chips are flip-chip attached onto the flex substrate, which is supported by a piece of glass, along with solder bumps for package I/O (see figure). After the chips are underfilled, the flex film is removed from the supporting glass. The film is then folded, and adhesive is applied at the necessary points to keep the module together. Other packages demonstrated include the flexPAC, developed by the Fraunhofer Institute IZM and the Technical University of Berlin (Berlin, Germany), and the F2-cPAC by Packaging Technologies GmbH (Pac Tech, Nauen, Germany). Both packages use a maskless meniscus bumping technique to bump the chips. An electroless Ni deposition of about 15 µm is followed by an Au/Sn solder deposition, also about 15 µm thick. Flip-chip attach to a flex interposer is performed using a fiber push connect technology. A modified wirebond head holds an optical fiber, which holds the flex substrate against the bump. Laser pulses are delivered to the solder ball through the fiber. IR emission from the solder goes back through the fiber to a detector for temperature monitoring.
Plasma Wafer ThinningTru-Si Technologies (Sunnyvale, Calif.) has developed a wafer thinning technology that can reduce the thickness of a silicon die to the 4-10 mil (100-250 µm) range for use in ultrathin packages. The Tru-Etch 2000 system uses the company's atmospheric downstream plasma (ADP) etching and wafer handling technologies to achieve those thicknesses. Existing wafer grinding processes can achieve thicknesses of 10-14 mils (250-350 µm), and they are subject to post grind stress and damage. The ADP process is said to have no stress or damage problems, and to have an ability to thin to less than 4 mils with very high uniformity. Current wafer etching and polishing processes, such as wet etch and chemical-mechanical polishing (CMP), use hazardous chemicals and large amounts of deionized water. ADP is a dry etch method designed to address those issues. Since it is a downstream process, there is no danger of plasma ion induced damage, and the company claims that frontside protection is not necessary. Also, since it is an atmospheric pressure process, there are no vacuum steps to reduce throughput. The process is said to be a highly repeatable and reproducible isotropic etch process that removes a uniform layer of silicon from the wafer. It also has high etch rates for common materials present on the backside of processed wafers, including silicon, silicon oxide, silicon nitride, polysilicon and BPSG. The company has also developed a wafer handling system to ensure protection of the frontside and edge of the wafer from damage during processing. |
