Advanced Forecasting Of Cost and Yield
A yield simulator accounts for the dynamics and costs of yield learning.
Pranab K. Nag, Wojciech Maly,Carnegie Mellon University; Hermann Jacobs, Siemens AG, Munich, Germany -- Semiconductor International, 7/1/1998
 |
At a Glance | | |
|
| ||
| |||
A few researchers have investigated yield learning in a semiconductor manufacturing line,3- 6 but the models applied do not capture the mechanics of yield learning itself. We developed a new methodology to predict defect-related yield, taking into consideration the operational aspects of manufacturing as well as the process of yield learning. Importantly, the model simulates interdomain dependencies among the areas of design, fabrication, test, inspection and failure analysis (FA), and their effects on yield, cost and productivity. The simulator, Y4 (Yield FOREcaster), reasonably replicates IC manufacturing line characteristics when subjectively compared with actual fab results. By simulating scenarios relevant to cost/revenue trade-offs, the model allows optimum dedication of resources in a fab.
Modeling methodology7-10
For the purpose of modeling yield learning, a manufacturing process can be viewed as consisting of two components: product fabrication and failure analysis. We will first concentrate on a single product manufacturing line. Let us also assume that there exists only one type of defect originating from a single source of particles (a piece of equipment). The hypothetical yield vs. time curve resembles the staircase function shown in Figure 1. Here, Tf is the time needed to detect and localize a failure, which leads to process intervention; Te is the time needed for a process correction and for the new process parameters to become effective; and Tr is the interval between the time that process correction is made and the time when yield improvement is realized. Thus, the total time required for yield change to occur is Tc = (Tf + Te + Tr) and the corresponding yield change, Yc.
 |
| Fig. 1. Net change in yield (Yc) occurs over the time between failure analysis (Tf), process correction (Te) and new process parameter establishment (Tr). |
Estimating Tr is roughly equivalent to estimating the cycle time for a process, starting from an intermediate process step where the correction is made until the last step of the process. Thus, it is the sum of the raw processing time and the queuing time that results when wafers must wait between process steps. A major contributor to queuing time is equipment downtime. The time factor Te may also contribute to equipment downtime, depending on the outcome of FA. Tf depends on a number of attributes associated with IC design, inspection methods and FA processes. The change in yield, Yc, on the other hand, depends on the correctness of the diagnosis and the efficiency with which contamination levels can be reduced as a result of corrective actions.
The yield learning process is described as a sequence of events starting with the introduction of particles, followed by defect source identification and concluding with complete (or partial) elimination of particles. Yield learning rate, therefore, depends on the following:
- The relationship between particles, defects and faults
- The ease of defect localization that in turn depends on the following:
- Size, layer and type of defect
- Ability to analyze the IC design
- Probability of occurrence of catastrophic defects
- The effectiveness of the corrective actions performed
- The timing of each of the events mentioned
- The rate of wafer movement through the process
An effective yield simulator should model the above factors. The simulator's primary goal is to track the sequence of events in a factory. Secondly, it must simulate the movement of the wafers in a fab line, representing such entities as product, process recipes, equipment, personnel and operating rules. Details of such modeling were addressed previously.8,9
Y4 simulation
 |
| Fig. 2. The heart of the simulator, the event handler, communicates with the wafer movement simulator (WSIM), the yield simulator (YSIM), the failure analysis simulator (FASIM), the particle monitor simulator (PSIM), the cost simulator (COSIM) and the probe test simulator (TSIM). |
The heart of the Y4 simulator is the event handler that communicates with six sub-modules: the wafer movement simulator (WSIM), the yield simulator (YSIM), the failure analysis simulator (FASIM), the in-line particle monitor simulator (PSIM), the cost simulator (COSIM) and the probe tester simulator (TSIM), as shown in Figure 2. The simulation control unit controls the operation of the event handler and the six modules. The user can implement different models using the tool kit of functions provided for modifying the common database for all the modules and the event handling routines. A basic user interface is available to read input files for the models, output the statistics gathered and customize the simulation control strategy.
The cost/yield models described previously8,9 have been implemented as internal models of the submodules (WSIM, FASIM, etc.). WSIM is similar to the commercial simulator ManSim,11 although the current implementation models only a subset of ManSim's operating rules and conditions. On the other hand, the number of external events that can be defined in ManSim is limited. Thus, Y4 was implemented with the ability to define events for particle introduction (PSIM), FA (FASIM), particle monitoring (PSIM), corrective actions (YSIM) and testing (TSIM).
In order to validate WSIM (the core of Y4), cycle time simulations were also conducted using ManSim, and the two were found to be within 1% of each other. Cost simulations confirmed the dependence of wafer cost on product mix, start rate, number of metal layers, etc. Details of these experiments, along with basic simulations of cycle times, test costs and yield distributions, are provided elsewhere.8
A spectrum of simulations demonstrates the ability of the Y4 simulator to model interactions between various design, fabrication, in-line monitoring and FA approaches. We used a 0.5 µí, three-metal CMOS process recipe. Because of its proprietary nature, cost data were scaled, and process recipes were modified. The recipe consists of 145 steps using 183 pieces of equipment for a capacity of 2496 wafer starts per week -- typical of a medium-sized factory. The lot size is 24 wafers, and thus the line capacity is 104 lots per week. The raw processing time is 302 hours.
We assumed the use of 150 mm wafers, accommodating 110 chips, 1.4 cm 2 in size. To simplify the analysis, four types of particles were considered, resulting in shorts in metal or polysilicon. The defect sensitivities (measured by critical areas as a function of defect size) for each defect type were derived by scaling results obtained from several CMOS designs in order to mimic a microprocessor- like product.12
 |
| Fig. 3. Resources for detecting polysilicon defects become available after Metal 3 yield reaches 65% (a) and 73% (b). |
Wafers were sampled for FA when there were more than 30 defective die on a wafer and fewer than three wafers were waiting to be analyzed. The FA was simulated as comprising five steps: observation under microscope, observation with scanning electron microscope, stripping layers (if required), cross-sectional analysis and spectroscopic analysis. The model parameters are set such that the maximum time required to analyze 30 defects in the top metal layer is about two weeks (not including the queuing time).
The weekly average of the yield trend plot is shown in Figure 3a, along with the yield of the polysilicon and Metal 3 layers. Metal 3 yield started to in-crease almost immediately after FA was initiated (after the 10th week). The polysilicon layer yield, on the other hand, started to increase only after another 15 weeks (around the 25th week). This reflects the fact that polysilicon defects are more difficult to detect than Metal 3 defects, which are nearer to the chip surface. In addition, the yield of Metal 3 is low enough during the first few weeks of FA that the resources are kept busy analyzing samples for metal defects. Polysilicon defects are, in effect, ignored until the Metal 3 yield reaches about 65%. However the rate of yield learning for the polysilicon layer is higher than that of Metal 3, since the increased availability of samples with polysilicon defects compensates for the difficulty in diagnosing these defects.
Figure 3b shows the results of yield simulation when the number of each type of FA equipment is doubled. In addition to the obvious increase in the yield learning, two more effects are apparent. First, polysilicon layer yield begins to increase around the 20th week -- approximately five weeks sooner than in the previous case. Second, at this point, the Metal 3 yield is higher than that in the earlier case (73% instead of 65%). There is enough FA capacity to allow for allocation of resources to the detection of polysilicon defects while the metal defects are being analyzed. The metal defects are also diagnosed more quickly.
Impact of sudden changes in yield
 |
| Fig. 4. The impact of a 5X increase in particles in week 30 is much less dramatic when FA capacity is doubled (b). |
In this series of simulations, a particle burst occurs in the end of the 30th week, causing a 5X increase in the mean of the particle number distribution in one of the seven sputtering tools. The net yield learning rate decreased (Figure 4a) compared to the result shown in Figure 3a. The increase in metal defects caused metal layer yield to drop first. After a certain delay, FA catches up with the increased number of defective die with metal defects, and metal yield starts to increase again. However, at the same time, the polysilicon yield learning rate drops, because FA resources are mostly consumed in detecting metal defects.
Figure 4b illustrates the same situation but with double the FA capacity. As expected, the yield learning rate is higher than in the simulation shown in Figure 3b; but there is an important difference between the two sets of yield learning curves. In Figure 4b, the yield learning rate of the polysilicon layer remains essentially unaffected. This result again illustrates that the extra capacity helps to perform analysis on polysilicon defects in spite of higher occurrence of defective die with metal defects. Also, at the time the yield problem occurs, metal yield is high enough that the number of defective die sampled for analysis is already low. Thus, the FA facility has little trouble absorbing the relatively small increase in the number of defective die with metal defects.
It is interesting to compare the two manufacturing lines -- one with a normal capacity and the other with doubled capacity of FA -- from the perspective of sensitivity toward yield degradation (Table 1). As expected, the manufacturing line with greater FA capacity is much less sensitive to the yield problem. Thus, any loss incurred because of the yield problem illustrated earlier is appreciably reduced in the second manufacturing line.
Finally, for argument's sake, we assumed that every IC produced could be sold at $100. The last two rows of Table 1 show the estimated profit in absolute value and as a percentage of the total investment, respectively. Comparing the case where there are no yield disturbances, one can see that an extra investment of $38 million in the FA facility increases profits by $355 million.
| Table 1. Cost and Profit Analysis | ||||||
| Normal capacity | Double capacity | |||||
| Undisturbed fab | With yield degradation | % Change | Undisturbed fab | With yield degradation | % Change | |
| Number of good die ($M) | 7.62 | 5.81 | -23.75 | 11.54 | 10.49 | -9.1 |
| Cost of die ($) | 72.52 | 94.92 | +29.92 | 51.13 | 56.90 | +11.28 |
| % Cost from failure analysis | 5.47 | 5.32 | -2.74 | 11.5 | 12.44 | +8.17 |
| Profit ($M) | 209 | 30 | -85.6 | 564 | 452 | -19.9 |
| Profit (% of investment) | 37.8 | 5.4 | - | 95.6 | 75.7 | - |
Impact of FA and particle monitors on yield learning
Particle monitors are employed with the expectation that a substantial fraction of in-process defects will be detected -- leading to faster yield ramps. In the least, particle monitors may identify critical areas of yield loss or detect out-of-control situations. But this technology has its limitations, including high equipment cost, questionable resolution below 1 µí particle size and reduction in wafer throughput. In fact, one can push the limits of resolution at the expense of throughput. To date, the impact of particle monitors on cost and yield (and thus productivity) has not been sufficiently studied.
Off-line failure analysis, however, has traditionally been the backbone of yield ramping. It is slow and can be expensive, yet it usually pinpoints the source of yield loss accurately. So while particle monitors can respond quickly to yield loss problems, results can be inaccurate. FA requires a longer cycle time but can be very effective in yield ramping.
In this example, a few changes were made to the simulation setup to reflect a more realistic manufacturing scenario. Assuming that there are 13 particle sources that result in 12 unique defect types leading to faults, four chips on three wafers were inspected at each level. The sampling strategy requires 16 scanners operating at 90% utilization. Process recipes were modified to include a particle-monitoring step following each step where particles were introduced. It was also assumed that defects in lower layers like active area and poly are more difficult to detect than defects in metal layers. Equipment cleaning was initiated when the average number of particles per die per lot exceeded a given threshold (20). Excess equipment downtime because of such activity was limited to a maximum of 5%.
 |
| Fig. 5. Rapid yield learning results when FA and particle monitoring are combined. |
Yield learning rates were compared using particle monitors only, off-line FA only and both techniques (Figure 5). Particle monitor use led to slow learning rates and low final yield. FA use led to higher ultimate yields but with slower learning rates. This is not surprising, considering that defect reduction because of FA was assumed to be up to 5X as effective as that using particle monitors (depending on the correctness of diagnosis). In combining the two yield ramping methods, we assumed that their effects were independent of each other under the constraint that the net equipment downtime that was due to equipment cleaning would not exceed 5%. Productivity and cost comparisons (Table 2) revealed that the lowest cost per good die and the highest yield ramping productivity are obtained when both techniques are employed. From a strategic point of view, timing is important, especially for short cycle time products such as ASICs. As shown, the time required to produce 2 million good die can be reduced from more than 36 weeks using only particle monitors and more than 25 weeks using FA to more than 20 weeks using both. The number of good die produced in 20 weeks nearly tripled when both techniques were implemented vs. particle monitors only.
| Table 2. | |||
| Particle monitors only | Failure analysis only | Both together | |
| Total number of good die (millions) | 2.14 | 4.45 | 5.65 |
| Cost of good die ($) | 137 | 78 | 65 |
| Total product cost ($M) | 359 | 342 | 371 |
| % Cost from FA | 0 | 3.48 | 3.24 |
| Time to reach 2 million good die (weeks) | 36.5 | 25.5 | 20 |
| Number of good die in 20 weeks (thousands) | 654 | 1094 | 2000 |
Conclusion
We used a discrete-event simulator, Y4, to estimate cost and yield of VLSI circuits as a function of time. The simulator integrates the key relationships governing the kinetics of fab operation. Such integration provides a powerful option for the crucial process of strategic manufacturing design and decision-making. Most importantly, the model is capable of simulating scenarios that are relevant to cost/revenue trade-off studies. It can be used to better facilitate factory design and capacity planning, product design and analysis, and FA strategies. These modeling activities represent a first step in interdisciplinary yield modeling, revealing a new frontier for yield and cost modeling.
Acknowledgments
This research was supported by SEMATECH grant MC-511 for Manufacturing Design Sciences. The authors would also like to thank Tyecin Inc., for providing the software ManSim, Alfred Kersch of Siemens AG in Munich, Steven Brown of SEMATECH in Austin and Darius Rohan of Texas Instruments in Dallas, for providing data, encouragement and feedback.
References
7. P.K. Nag and W. Maly, "Yield Learning Simulation," Proc. of SRC TECHCON '93, Oct. 1993, p. 280.
8. P.K. Nag, "Yield Forecasting," Ph.D. Dissertation, Carnegie Mellon University, April 1996.
10. Y4 Project WWW Documentation at http:www.ece.cmu.edu/~maly/yield/Y4/Y4.asp
11. ManSim X user manual, Tyecin Systems Inc., San Jose, Calif., 1995.
| Pranab K. Nag is a post doctoral research fellow at Carnegie Mellon University in Pittsburgh, Pa. He received his master's degree and doctorate in electrical and computer engineering from Carnegie Mellon University and his B.Tech degree in electrical engineering from the Indian Institute of Technology (Kharagpur, India). Phone: (412) 268-6642 Fax: (412) 268-3204 E-mail: pkn@ece.cmu.edu |
| Wojciech Maly is a Whitaker Professor of electrical and computer engineering at Carnegie Mellon University, where he has worked since 1983. Maly's research focuses on the interfaces between VLSI design, testing and manufacturing with emphasis on the stochastic nature of phenomena relating to these three VLSI domains. He has a doctorate from the Institute of Applied Cybernetics, Polish Academy of Sciences in Warsaw, Poland, and a master's degree in electronic engineering from the Technical University of Warsaw. Phone: (412) 268-6637 Fax: (412) 268-3204 E-mail: maly@ece.cmu.edu |
| Dr. Hermann Jacobs is director of the Silicon Process and Materials Department at Siemens Semiconductor in Munich, Germany, with worldwide responsibility for silicon and GaAs wafer material and process chemicals. He received the Borchers Award for Outstanding Ph.D. thesis from the Technical University of Aachen, where he previously received the Diploma Degree in solid state physics. Phone: (49) 89-636-45752 Fax: (49) 89-636-48666 E-mail: hermann.jacobs@hlistc.siemens.de |
