Impact of Lot Buffering on Overall Equipment Effectiveness

		At a Glance
	Lot buffering significantly improves the utilization of a piece of equipment and dramatically increases its productivity. It also improves the efficiency of other in-line tools by reducing the operator per tool ratio for a specific tool.

Lot buffering, adding extra cassette stations with automatic feed to wafer processing equipment, is shown through a case study to have a significant impact on productivity of a fab with little or no increase in capital investment.

As semiconductor technology continues its rapid advancement, semiconductor fab costs skyrocket, and their effective lifetime decreases. In the mid-1980s, a fab cost about $100 million and had an extended life span of nearly 10 years. Now, there are billion-dollar fabs with a life span of only five years. The depreciation alone on a typical billion-dollar fab is $4 million a week.¹ This trend puts serious pressure on integrated circuit (IC) manufacturers' profitability and threatens to derail Moore's Law.

In order to realize continued profitability, the semiconductor industry faces two alternatives. It can slow down the pace of advancement to increase the lifetime of capital investments and devote more resources to productivity improvements rather than technology advancements. Or, it can focus on improving fab productivity as advances in semiconductor technology continue at its current fervent pace.

The first alternative is not only undesirable, it is an impossibility. Someone always will be driving technology to gain a competitive advantage, and the rest of the industry would be forced to follow suit. IC manufacturers clearly must boost fab productivity simultaneous to IC technology advancement.

As a comprehensive measure of fab efficiency, overall equipment effectiveness (OEE) has been adopted by SEMATECH and is gaining popularity as a tool to drive equipment productivity improvements. It is currently being used by several leading IC companies such as AMD, IBM, Lucent Technologies, Motorola, National Semiconductor and Texas Instruments, among others.² It was originally developed in Japan as part of the total productive manufacturing (TPM) program.³ OEE is a comprehensive measure that compares actual throughput to the maximum possible productive throughput (throughput of good product). This measure groups all productivity losses into three categories: availability, performance efficiency and quality of output.   

Fig. 1. In new fabs, the average equipment's overall equipment effectiveness (OEE) runs about 30% (Source: SEMATECH).

SEMATECH estimates that in new fabs, the average equipment's OEE runs about 30%² (Fig. 1). Bottleneck tools run at 45% OEE⁴ (non-bottleneck tools have excess capacity and are therefore less effective). SEMATECH states that reasonable OEE objectives are 65% for the average tool and 85% for the bottleneck.² Thus, the potential for efficiency gains is tremendous, translating directly into profitability. For example, in a 5000 wafer starts per week (wspw) fab, an increase in OEE of the bottleneck tool from 45% to 50% results in an additional $25 million in net profits per year because of the increased capacity (assuming $2000 revenue and $1000 cost per wafer). Additionally, with each generation of semiconductors, the manufacturing equipment gets more complicated and costly.

A significant push to improve OEE is necessary to keep the situation from getting worse. With a focus on OEE, IC manufacturers can improve profitability in an increasingly competitive and crowded industry that faces escalating capital costs and reduced lifetime of those capital investments.

Lot buffering

Fig. 2a. & Fig. 2b. Shown is the top view of PEP and PEP Queue with two and six cassette stations, respectively. Red arrows indicate rotation of cassettes, and purple arrows indicate flow of wafers. Wafers can go from either cassette in the WHM to either PCM, depending on operator setting.

Integrating lot buffering capability into a tool is one way to improve OEE of a semiconductor fab. Although lot buffering has its most dramatic impact when applied to the bottleneck tool in the fab, the effectiveness of buffering is not limited to the bottleneck tool. Buffering even non-bottleneck tools in-creases the OEE of not only the buffered tool, but the entire equipment bay. Fab capacity increases without adding a single tool. Additionally, capital investment is potentially reduced, since in some instances fewer tools are required.

Study method

A case study recently completed by GaSonics International and TEFEN USA shows the impact of buffering on a fab through buffering a photoresist removal tool. Even though these are rarely bottleneck tools, buffering photoresist removal tools proved to have considerable impact on fab OEE with little or no increase in capital investment. The study used GaSonics' PEP (Performance Enhancement Platform), a single-wafer photoresist removal system with two independent chambers, and PEP Queue, a buffered PEP, which increases the number of cassettes that can be loaded and run from two to six (Fig. 2).

The model used for this study was developed in four steps. First, a time study of the standard PEP and PEP Queue was performed using tools in GaSonics' lab and in production at a major DRAM manufacturer. Second, data of the relevant tools (Table 1) were accumulated from 12 major DRAM and logic fabs in the United States, Asia and Europe and combined into one set of representative benchmark data. Next, a capacity model was built to determine the tool requirements for the bay. Finally, all data were entered into WITNESS software, and the model was run. (WITNESS is a business process simulation package available from Lanner Group.) The study was conducted separately for the etch and implant bays.

The study assumed a typical fab with 5000 wspw. Based on the benchmark data referred to above, the model also assumes 10 photoresist removal steps in the implant area and six photoresist removal steps in the etch area. One operator controls three to four tools (the actual ratio of operators to tools is TEFEN's proprietary benchmark data) in both the implant and the etch areas. The availability and throughput of the equipment in those areas, based on the benchmark data, is shown in Table 1.

Table 1. Benchmark Data
Tool	Availability	System throughput (when system available)
Implanter	69%	63.5 wph
Etcher	79%	35 wph
Clean deck	90%	180 wph
GaSonics standard PEP (30 sec process)	89%	107 wph
Operator	75%	--

These numbers are the actual throughput of the tool when it is available for processing. Since these throughput numbers include fab production inefficiencies, they are less than the maximum theoretical throughput quoted by the tool manufacturers. For example, the nominal throughput for PEP running a standard process is 140 wph. As these numbers do not include non-available time, they are higher than the numbers that follow in the rest of the study (a 30 sec photoresist removal process time was assumed throughout the study).

Results and discussion

Using actual production conditions, the simulation model found that in parallel mode -- the most common mode of operation in which both chambers run the same process recipe simultaneously -- the throughput of the photoresist removal tool in the implant area increases slightly from 105 wph to 108 wph with the buffer. The increase is 14%, from 86 wph to 98 wph, in the etch area. Throughput increases because of reduced wait for operator time. Wait for operator drops from 7% to 3% in the implant area, raising OEE of the photoresist removal system from 72% to 74%. In the etch area, the wait for operator is cut from 18% to 8%, increasing OEE from 59% to 67%.

The improvement in throughput is even more dramatic when the equipment is run in independent mode rather than in parallel. In independent mode, each chamber on the system runs a different recipe; the left cassette feeds the left chamber and the right cassette feeds the right chamber. Throughput increases 23% and 42%, respectively, for implant and etch areas, approaching the throughput of parallel mode operation. Because the buffered system allows independent recipe selection of each cassette on the system, it imposes no limitation on process flexibility. Unlike parallel mode, a standard two-chamber system cannot run continuously in independent mode because one cassette feeds a single chamber running an independent process. Each cassette cannot be removed until all the wafers have been processed. The buffer is necessary to keep the tool running continuously. Naturally, no fab can keep the tool running 100% of the time, but the ability to run continuously allows for lot cascading (running continuously for extended periods of time), which has a significant impact on throughput.

With the increase in efficiency that the buffer brings, more fabs will be able to run in independent mode. This is of particular interest to fabs running mixed devices. This mode offers tremendous processing flexibility, but until now, some fabs have hesitated to use independent mode because of its inefficiencies, particularly when running two different process times. This study assumes 30 sec process times in each chamber, but in independent mode, different process times are likely. For a standard system, the operator must attend the tool when each cassette finishes processing for maximum utilization, which will be at a different time for each module of the tool. With the buffer, the throughput and OEE of the system approach that of parallel mode, significantly improving productivity of independent operation - espec ially for different process times. This makes independent mode operation a much more attractive option for users, increasing the processing options available.

Because of the throughput increase the buffer provides, the number of systems necessary may be reduced, depending on the wafer starts and flow of a given fab. In this study, the number of photoresist removal tools needed in the implant and etch areas for independent operation were four and three, respectively. Adding the buffer lessened the number of tools needed by one in each area. Since the buffer adds only 25% to base system cost, respective reductions in capital investment of 25% and 50% of the standard system cost are achieved. The reduced tool set also reduces cleanroom space and overall running cost. Similar results can be achieved in parallel mode depending on wafer starts and fab flow. In this study, no change in the number of tools required in either bay was achieved for 5000 wspw when running in parallel. However, at 7000 wspw in the implant area, system requirements are re-duced from five to four. In the etch area, system requirements are reduced by one from two to one at 3000 wspm and from three to two at 6000 wspw.

While photoresist removal tools are already relatively low-cost, high-throughput tools, buffering them has several advantages:

• Increasing throughput brings potential reductions in tool sets.
• If the tool is downstream from the bottleneck, it improves cycle time.
• If the tool is upstream of the bottleneck, it allows reduced work in process (WIP) in front of the bottleneck.
• Because of various fab flow issues, any tool can become a bottleneck short term. If this temporary bottleneck is buffered, it offers the fab a big advantage.

However, the most significant impact in productivity and, ultimately, profitability, is the effect on OEE within the entire bay that contains the photoresist removal tool. Because the buffer demands less operator attendance, operators are free to focus on the bottleneck tools in the equipment bay.

For the implanter, the wait for operator dropped from 9% to 5% and OEE rose from 53% to 56% when the buffer was added to the photoresist removal tool running in parallel mode. The resulting increase in throughput per tool from 40 wph to 42 wph allowed the bay to produce 1100 additional wafers per month. (By the Theory of Constraints, the throughput and OEE of the bay are equal to the throughput and OEE of the bottleneck tool.³) In the etch area, the wait for operator was reduced from 12% to 9%, and OEE improved from 63% to 66%. Actual throughput per tool increased from 23 wph to 24 wph, producing an additional 860 wafer starts per month for the etch area. If the etch area is the major bottleneck in the fab, this means that a fab can produce 4.25% more wafers per month, resulting in $20 million more revenue (with little or no additional fixed cost) per year (assuming $2000 per wafer), simply by adding buffers to its photoresist removal systems.

Similar results to those with the photoresist removal tool running in parallel in the implant and etch bays are also obtained with the tool running in independent mode. All the study results are summarized in Tables 2 and 3.

Three factors drive the efficiency improvements realized by the buffers:

• Loading time becomes internal to the buffered tool, rather than external
• Wait for operator because of operator interference (when demand of an empty tool interferes with the operator's other work) declines
• Loading several batches is more efficient for the operator than loading one cassette at a time

Note that not all the reduction in wait for operator translates directly to improved OEE. Some reduction transfers to wait for WIP.

Reductions in operator interference represent a major operational efficiency improvement. For example, at 107 wph, the standard photoresist removal tool takes 28 min to run two cassettes. An operator must attend the machine about twice per hour to change the cassettes and keep the tool running near full capacity. To attain maximum throughput, the photoresist removal tool in the study can operate continuously in parallel mode in both buffered and standard configurations. However, to do this with the standard configured system, the operator would have to attend the tool an average of every 14 min within a 14 min window to remove the finished cassette, and replace it with a new cassette while the second cassette is still processing. With the buffer, visits to the tool are only needed once every 70 min within a 14 min window to maintain continuous mode.

The buffer also increases flexibility in the loading sequence, enabling optimization of operator movement. The window during which the operator has to visit the tool extends from 14 min to 70 min, if the operator can visit the tool more often. This balance between the number of visits and the size of the time window to perform these visits can be optimized for the greatest efficiency of the particular manufacturing situation.

Conclusion

Increasing productivity by focusing on ways to improve OEE is receiving a lot of attention. The need to improve OEE and the impact of lot buffering on OEE is significant enough that I300I is including buffering as a guideline in 300 mm equipment design for batch-type equipment and single-wafer equipment with high throughput: Lot buffers shall be implemented by tool suppliers so tools can run nonstop between lots.⁵ For existing semiconductor fabs, retrofitability is key.

Lot buffering significantly improves the OEE of not only the buffered tool, but the entire equipment bay. It improves the throughput of the buffered tool and greatly increases operator flexibility by reducing the tool's operator interference. It is one way equipment makers can help the semiconductor industry push their fabs to be more productive, continuing the trend of providing increasingly advanced devices while simultaneously reducing their cost.

References

1. Doubling Capital Effectiveness, Feb. 11, 1997, Stuart McIntosh.

2. SEMATECH Overall Equipment Effectiveness training course.

3. Meyersdorf, D. and J. Fowler, "Improving Equipment Productivity," TEFEN Ltd. SEMI Education Class, SEMICON West, July 1997.

4. SIA (1997) National Technology Roadmap, Semiconductor Industry Association.

5. I300I Factory Guidelines: Version 2.0, Dec. 12, 1997.