A Cost-of-Ownership Study On Lithography Systems

		At a Glance
	Cost-of-ownership on lithography systems that may be used for future 1-4Gb DRAM level fabrication is analyzed. The studies include optical lithography using KrF or ArF lasers, X-ray proximity lithography and projection electron beam (EB). Key factors covered are equipment costs, throughput, mask cost and resist/process costs. It is shown that the X-ray has the potential for being economically superior to ArF lithography in volume production of 3 million chips per month.

It is widely accepted that lithography is key for further reduction of ULSI device pattern dimensions. In selecting the lithography tool to be used in fabricating 1-4Gb DRAM level devices, alternatives to optical lithography need to be considered. The first generation of these devices will have design rules of 0.18 µm (180 nm) and 0.13 µm (130 nm), respectively, and further reduction will be required for each generation to be cost-effective.

Optical lithography using KrF lasers will be a useful technique. However, to obtain a reasonable process margin at 0.18 µm and below, contrast enhancement technologies such as modified illumination, phase shift masks and optical proximity correction will have to be employed. ArF lithography is being developed, but it is still unclear whether the related technologies such as optics materials, lasers and resists can meet the required specifications. All these can potentially increase costs.

To sort through the issues and to determine cost-effective solutions, cost-of-ownership (COO) analysis has been performed on optical lithography as well as two non-optical technologies: X-ray proximity lithography using synchrotron radiation (SR),¹ and electron beam (EB) character projection (CP).² Other non-optical techniques such as EUV,³ SCALPEL⁴ and ion beam projection lithography are not included in this work. Since the technology bases of these technologies are rapidly growing, studies elsewhere are warranted. Among the COO studies on lithography technology,^5-7 this paper is an updated version of one of them.⁷

COO model

The total lithography cost is given by the following:
where C_lph is the lithography system cost ($/hr), T_net is the net throughput (wafers/hr), N_c is the number of chips on a wafer, C_res is the resist and related process cost per wafer, C_msk is the mask cost and N_w is the total number of wafers exposed by a mask. The former analyses have expressed C_tot in terms of wafer level exposure. Here, we propose to use chip level exposure (CLE) to make comparisons in different wafer and chip sizes.

To calculate the lithography system cost, the following equation is used:
where C_sys is the cost of a machine, Y is the depreciation time (hr), b is the coefficient to describe the cost for operation and maintenance (that we hereafter call the O/M coefficient), T_y is the operating time (hr) per year, C_f is the cleanroom cost, A_cr is the footprint of the machine and C_lb is the labor cost. In the case of X-ray lithography, the term C_sr/Y_sr, where C_sr is the cost of the S_R accelerator building and Y_sr is the depreciation time for the building, is added to Equation 2.

The resist and the related process cost is given by the following:
where G_res is the resist cost per gallon (G), W_g is the number of wafers coated per gallon and C_pr is the cost of the machines for additional processes in the case of optical lithography.

To discuss the mask cost, it was apparent that a set of COO models for the mask fabrication process⁸ was needed. Since this is a complicated issue, we determined that this should be treated elsewhere. Instead, a simple assumption on the mask cost is used.

Throughput models

The throughput of the KrF and ArF exposure tools, which is assumed to be step-and-scan systems with respect to masks and wafers, is given by the following:

where P_s is the laser pulse per slit, S_f is the field size in the scanning direction, S_w is the scan slit in the shorter length, L_f is the laser frequency, W_s is the time for step motion, N_e is the number of exposures per wafer and W_e is the overhead time for wafer load/unload and pre-alignment. The time for acceleration corresponding to one slit scan is taken into account.

Similarly, the throughput of X-ray steppers is given by the following:

where F_r is the resist sensitivity and P_x is the average SR power throughout exposure field. X-ray lithography may employ a full field or a scanning-type exposure illumination system. In this study, the latter scanning system is used where P_x is given by the following:

P_x is the exposure power in a reference 50 mm x 50 mm field, and an over-scan of 10 mm was assumed. The ability to cover a large exposure field suggests that this kind of illumination system can be used in multiple device generations.

Lastly, the throughput of EB character projection is given by the following: 

where S_wa is the total character shot number per wafer; F _e is the EB deflection frequency (Hz) and is the coefficient that describes overhead time for beam calibration, alignment and stage movement in each chip exposure.

Optical lithography

The parameters used for COO analysis on optical steppers is shown in Table 1. A KrF and ArF scanner is used for 1Gb and 4Gb DRAM levels, respectively. To show the continuity from present technologies, an i-line stepper for 64Mb technologies and KrF stepper for 256Mb are also included. The chip size was taken from the 1997 version of the SIA Roadmap, showing 25 x 16 mm² for 1Gb first generation and 25 x 23 mm² for 4Gb. The chip width is kept at 25 mm so that the stepper optics design is feasible. The laser frequency for the KrF system for the 1Gb generation is 1 kHz, and the laser pulse per a scanning slit is 40, indicating that the laser is higher in power and more stable than the present one. The laser frequency for the 4Gb ArF is 800 Hz, and the pulse per slit is 50, which are also the case in 256Mb KrF.

The overhead time for wafer load/unload and alignment is assumed to be 25 sec. The raw throughput thus obtained is 59 200 mm wafers/hr for 256Mb design rules, 47 300 mm wafers/hr for 1Gb and 48 300 mm wafers/hr for 4Gb. To obtain net throughput, raw values are multiplied by a factor of 0.72 (0.8 for the machine itself and 0.9 for the cleanroom). The cost of steppers, which are for volume production, is assumed to be $5 million, $7 million and $9 million for 256Mb, 1Gb and 4Gb design rules, respectively. To calculate the system cost, the depreciation time of five years is assumed throughout this article, unless otherwise stated. The cost of operations and maintenance (O/M) coefficient is set to be 5% for i-line and 7% for ArF to account for the fact that more maintenance will be necessary in advanced lasers.

X-ray lithography

Table 2. Parameters for X-Ray Lithography Cost Estimation
	1Gb	4Gb
Chip size (mm 2)	28 x 14	34 x 17
Exposure/wafer	80	52
Scan length for two chips (mm)	38	44
SR power on wafer (mW/cm2)	79	68
Exposure time (sec)	0.51	0.59
Step time (sec)	0.4	0.4
Overhead time (sec)	25	25
Raw throughput	37	47
Stepper cost ($M)	6	7
Stepper and beam line footprint (ft2)	300	300
O/M coefficient (%)	3	3

The parameters used for COO analysis of the X-ray steppers are shown in Table 2. Since X-ray lithography can provide an adequate exposure area, the chip size is chosen to be 1x0.5 mm² and has the same area as the one for optical steppers in each generation. It has been shown that in a typical scanning beam line, the condition of P_xo = 50 mW/cm² can be attained.⁹

The resist sensitivity anticipated is 40 mJ/cm², which is a factor two to five higher than the currently available resists. Assuming the same overhead time as in the optical steppers, the raw throughput was determined to be 37 for 1Gb and 47 for 4Gb. The X-ray steppers cost $6 million and $7 million, respectively, somewhat lower when compared with the optical scanners because of the absence of reduction optics and light sources. The O/M coefficient is 3%, reflecting less operation power and maintenance.

For the accelerators and beam lines, the parameters used in the analysis are shown in Table 3. The cost is ~$20 million for a storage ring and injector and $0.7 million for a beam line, assuming a simple one-mirror system.⁹ The depreciation time of these parts is 10 years. The cost and the depreciation of accelerator building are $10 million and 30 years, respectively. The O/M coefficient of beam line and accelerator are 3% and 5%, respectively.

E-beam lithography

The parameters used for estimating the throughput of EB character projection are shown in Table 4. The average total shots of various device layers is set to be 2x10⁹ for 300 mm wafers, based on 9x10⁸ for 200 mm wafers with a 5 MHz deflection frequency in a subfield. Settling time is typically 50 ns, EB current density is 20 A/cm² and resist sensitivity 3 C/cm ². It is further assumed that half the required subfield writing time is additionally used for beam settling in main-field deflection, beam calibration, alignment to underlayer marks and stage motion.

The throughput thus obtained is 12 200 mm wafers/hr and 5.8 300 mm wafers/hr. In the latter case of 5.8 wafers/hr, the cost of the exposure tool is assumed to be $6.5 million for 1Gb and $8 million for 4Gb, taking into account the increase with wafer size, writing accuracy and data volume. The machine footprint is 160 ft², and the O/M coefficient is 4%.

Resist costs

Tables 5 and 6 list the parameters used for COO estimations of resists and related processes. While KrF resists have seen initial use in volume production, it is not yet clear how much of its cost will be reduced in the future. Nevertheless, it is assumed that KrF resist costs will be reduced to twice that of i-line, which also applies to X-ray and EB resists. As for ArF resists, the material costs will be high, but the resist is assumed to be more or less determined by the quality of management, lessening the cost differences between KrF and ArF. Thus, ArF costs are chosen to be 1.5 times that of KrF costs.

Resist usage is assumed to be 4 ml for a 200 mm wafer and 6 ml for 300 mm. The throughput of coat/developer is assumed to match each stepper, except for EB projection, which is set at 40 wafers/hr. The coat/developer costs are included with those of the exposure tools. As for additional processes related to KrF and ArF resists, the use of bottom anti-reflection (AR) coatings and chemical-mechanical polishing (CMP) are assumed. The net throughput of these technologies is assumed to be 40/hr, with an O/M coefficient of 5%.

Mask costs

Table 6. Additional Process Cost Parameters for Optical Resists
Wafer size	200 mm	300 mm
BARC deposition system ($M)	1.1	1.4
Footprint (ft 2)	70	90
BARC etch system ($M)	0.9	1.2
Footprint (ft 2)	60	80
CMP system ($M)	1.3	1.7
Footprint (ft 2)	80	100

Mask costs (Table 7) assume a 1.5 increase in each generation. This is a crude extrapolation based on the trend of optical mask cost variations. The optical mask cost is $8000 for 16Mb technologies and $41,000 for 4Gb. In contrast to optical masks, X-ray masks require less exposure proximity correction in patterned features, and the EB current density in X-ray mask writers can be higher because of smaller writing sizes. These mean less EB writing time, suggesting that X-ray masks may be less expensive. Nevertheless, for simplicity, the same cost is used in both mask technologies for 1Gb and 4Gb generations.

Labor costs

Labor cost parameters are listed in Table 8. It is assumed that one one-half person is assigned per stepper for any operation in the cleanroom. The number is reduced to one-fourth in EB machines because of lower throughput. The labor cost is $30/hr. The cleanroom cost is $500/ft² per year, which is rather high, because the footprint of the machines was determined according to net values. The operation time was defined on a 24 hrs/day, 350 days/year.

COO comparisons

Summarized in Figure 1, the optical lithography costs for 200 mm wafers are $0.035/CLE with 64Mb i-line technology and increase to $0.1/CLE with 256Mb KrF. The largest contribution to this increase is resist/process costs. Surprisingly, when using 300 mm wafers and increasing laser capability, the cost for 1Gb design rules using either KrF or X-ray is slightly less. The cost for 4Gb by ArF, however, is increased to $0.18/CLE, whereas 4Gb by X-ray is 30% less than this value because of lower system and resist/process costs.

Fig. 1. Assuming 40,000 wafers/mask, 200 mm wafers for i-line and 256Mb KrF steppers and 300 mm wafers for the others indicate cost savings with X-ray lithography over that of ArF.

A volume production of 3 million chips/month with 10 critical layers is assumed. The number of required X-ray steppers are 11 and 13 for 1Gb and 4Gb, respectively. We assume that these exposure tools can share a single set of accelerators. The total number of wafers processed by one mask is assumed to be 40,000, making mask costs very small. Note that these costs are net values, and gross values are obtained by taking into account yield, cost for metrology and wafer transportation, particularly for 300 mm wafers. 

Table 9 indicates the difference in the resist/process costs among X-ray, KrF and ArF technologies for 300 mm wafers. The values are $2.5, $5.1 and $6.2 per wafer, respectively. The difference between X-ray and KrF is primarily because of AR coatings and CMP processes, and the cost difference between KrF and ArF is due to resist costs. In stating these assertions, only one-third of the AR coating and CMP costs are applied here, and the rest can be carried out in intrinsic wafer processes. To account for disposals such as polishing materials and pads for CMP, $0.7/wafer was added.

Table 9. Resist and Related Process Cost in KrF, ArF and X-ray ($/wafer)
	KrF	ArF	X-ray
Resist	2.5	3.6	2.5
BARC	1.8	1.8	--
CMP	0.76	0.76	--
Total	5.1	6.2	2.5

Cost comparisons to operate KrF, ArF or X-ray steppers for 1Gb and 4Gb are shown in Table 10. Table 11 indicates that when using X-ray lithography, the cost per stepper is rather small because of the number of steppers linked to an acerlerator and longer depreciation times. Adding the bottom values in Table 11 to each of the X-ray steppers in Table 10, the total cost of stepper operation for 1Gb is similar to that of KrF, whereas the one for 4Gb, using X-ray is 13% less than with ArF. Note that if more than six steppers are linked to the accelerator, operation costs including accelerators are less than for ArF scanners.

In Figure 2, the cost of EB character projection is compared with that of KrF, ArF and X-ray lithography at 1Gb and 4Gb. Here, 500 wafers/mask is assumed possible in ASIC-type production. When applying this condition, the cost of EB lithography is comparable to that of optical or X-ray lithographies. We assumed that the cost of CP apertures are part of the tool cost except with special shapes, which adds $1000 for each production. It should be mentioned that the 500 wafers/mask condition can easily change depending on the machine cost and throughput.

Fig. 2. Comparison of EB character projection to KrF, ArF and X-ray with shared accelerator costs at 500 wafers/mask show a high percentage of the costs going to the masks.

The COO analysis of lithography systems for future 1Gb and 4Gb DRAM level fabrication indicates that X-ray lithography has the potential of being economically advantageous in comparison to optical. However, in the presence of rapid technology evolution in both optical and non-optical lithographies, further COO studies are necessary.

Acknowledgments

This study is based on collaborative work performed in the application of synchrotron radiation to the semiconductors research group at the Japan Technology Transfer Association. The research group is supported by about 20 member companies. The authors worked together with N. Atoda, formerly at SORTEC, M. Hirose from Sumitomo Heavy Industry, S. Ishihara from NTT, H. Nagata from Nikon, S. Ohki from NTT Advanced Technology Corp., K. Suzuki from NEC and M. Yamabe from Fujitsu. The authors also would like to thank H. Ikeda and Y. Sakai, former chairman of the research group, for continuous encouragement.

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3. R.H. Stulen, JSPE Proceedings on Soft X-ray Optics 1997, The Japanese Society for Precision Engineering, p. 5.

4. L.R. Harriott, et al., Microelectric Eng. 35 (1997) 477.

5. G.C. Escher, presented at International Workshop on High Throughput Charged Particle Lithography, Aug. 17, 1994.

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