SEMICON West 98: A Continuing Focus on Productivity
SI Editors -- Semiconductor International, 7/1/1998
Capabilities of optical lithography, both i-line and DUV, are being pushed as much as possible through optical enhancements and phase-shifting masks. During the past six months, progress in extending optical lithography with enhancements below 100 nm has been impressive. Non-optical approaches such as X-ray and e-beam lithography, however, are also making headway. A recent COO analysis out of Japan has indicated that X-ray lithography may have the potential of being economically superior compared with optical in a volume production of 3 million chips per month.
The 300 mm generation continues to push new technologies from lithography to cleaning techniques. Standards appear to be a pressing issue facing the industry. Currently there are four "standards" for 300 mm reticle carriers -- with three from the Pacific Rim. Decisions will impact designs for I/O ports of all 300 mm wafer processing tools.
Wafer processing
The biggest challenge in ion implantation remains the formation of the lightly doped drain (LDD) region (actually, it has become more a medium doped drain or MDD) on the p-channel transistor. Although several techniques are in development, such as gas immersion laser doping (GILD), it appears as if traditional mass accelerated ion im-plantation will be able to meet the needs of ultrashallow LDD/MDD p-channel implants. New systems will be introduced at SEMICON West that have the ability to implant boron and BF2 at energies as low as 200 eV. In older systems, it was difficult to generate adequate current densities at energy levels much below 5 keV. Recent studies have shown that traditional ion implantation techniques should be extendible to the 0.10 µm generation. At that time, it might be necessary to go to an alternative transistor design, such as one with raised source/drains. In the transistor stack (gate and gate oxide), the main focus will be on ways to improve gate oxide performance while making it thinner. Oxynitride gate dielectrics are quite promising and should be an interesting topic of discussion among suppliers of RTP and furnace system manufacturers.
Major changes are under way in the area of interconnects -- the on-chip "wires" that connect transistors and memory cells and I/O pads. The big change is that the industry is beginning a transition from aluminum to copper as the main interconnect material. Work is also under way on a reliable material with a low dielectric constant (called low-k dielectrics) to insulate between the metal lines. Copper will most likely be patterned with a dual damascene approach, where a planar oxide is deposited and the holes and trenches are etched and then filled with copper. This is because copper is difficult (but not totally impossible) to etch. Tungsten plugs will be used only at the contact level. The copper will most likely be deposited with an electroplating method, although PVD will still be used to deposit a copper seed layer, as well as an underlying diffusion layer, typically tantalum, tantalum-nitride or possibly tungsten-nitride.
Beyond the challenges of copper fill, dual damascene creates some interesting challenges for oxide etch because of the very high aspect ratios, as well as copper chemical-mechanical polishing (CMP), since the tantalum barrier that is polished at the same time is much harder than copper. At SEMICON West, we expect to see a variety of new products designed to meet the copper/low-k dielectric/dual-damascene challenges.
Metrology trends
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| Fig. 2. Production tools for 300 mm wafer processing, like the Millennia multimodule platform for resist and isotropic etch, will be prominent at SEMICON West 98. (Source: Gasonics) |
Products in the field of test, measurement and inspection continue to closely follow the SIA Roadmap. Software-based fault localization tools compatible with major test methodologies are evolving rapidly, and present at SEMICON West will be not only new products in this field, but -- enabled by sophisticated software -- new uses for already existing tools. This is taking place not only in the areas of defect analysis, but also in process control. This year's event will show that the trend can be expected to continue and become steeper, as expert systems continue to take over metrology and defect inspection, complementing and supplementing existing and newer tools. More and more, human intervention is being needed less and less.
New and enhanced products exhibited at the show will range from defect inspectors designed to address new problems such as accelerated shrinks and DUV lithography -- which now requires that its high-performance reticles be inspected for contamination -- to others meeting the challenges of advanced interconnects, shallow-trench isolation, low-k dielectrics and damascene processes. A corollary of the latter is the appearance of patterned-wafer inspection systems for production-line monitoring, specifically in the areas of CMP inspection.
This SEMICON West will also reflect the continuing move from optical to CD-SEM for defect classification purposes. This is stimulated by the latter's higher resolution and tilt capabilities, with the final touch being ADC expert-system software, which increases exponentially the tool's power.
Clean processing
Controlling contamination in all aspects of processing continues to gain importance as such contaminants become the larger components of yield loss in the most advanced fabs. Improved solutions for post-CMP wafer cleaning will be shown by the manufacturers of wafer cleaning tools and CMP system manufacturers. Wafer cleaning tools are also delivering higher efficiency cleaning requiring lower quantities of chemicals and DI water, as well as more compact designs for lower cost cleaning of 200 mm and 300 mm wafers. Fab upgrades using minienvironments are becoming common as fab managers around the world become more convinced of the benefits of wafer isolation. More efficient methods for fab automation will also be presented at the show, as they also play a key role in contamination control.
Environmental issues and "green" processing are being addressed, especially by the suppliers of gases and chemicals, but also by the manufacturers of delivery and treatment systems. Look for ISO 14000 compliance -- similar to ISO 9000 -- but addressing environmental responsibility in the semiconductor industry.
Yield management
As the time between technology transitions continues to shorten and competition among semiconductor suppliers intensifies, time-to-market has become increasingly critical. Enabling solutions for improving yields more quickly will be offered by an increasing number of companies involved in all areas of wafer processing, assembly and testing.
Many equipment and materials' suppliers will also be showing how they capitalize on delivering technology that enhances yields. Though this has been an important focus of companies in the past, many can now quantify such yield improvements.
Traditional suppliers of yield management solutions continue to increase their services to the fab for holistic yield management. Both software and hardware tools are addressing needs for more comprehensive data management, defect localization and faster means of tracing defects to their sources. The link between yield management at wafer processing and after final testing of the packaged devices is becoming more critical, too, as companies continue to improve device quality.
Assembly and packaging
Two major trends are emerging in the area of assembly and packaging. One is the blurring of the line between chip and package, and the other is increased automation.
The blurring of the line between chip and package is taking many forms. There are already a handful of wafer level packaging products or processes in existence, and for two of them, the "package" is simply a redistribution layer that passes typical packaging reliability tests. Also, the chip and package are becoming so interdependent that they must be designed together to a certain degree. Suppliers exhibiting at SEMICON West will be featuring solutions that address these needs. Blurring is also happening between the package and the circuit board. The flip-chip onto laminate model that the SIA Roadmap points to is essentially a miniature circuit board. Plans are in place to leverage existing board assembly technology for packaging.
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| Fig. 3. An increasing number of "packages" are simply a layer of redistribution material that passes JEDEC tests. (Source: Flip Chip Technologies) |
Automation is finding its way into packaging operations. More are using the same manufacturing execution systems (MESs) that wafer processing operations use. There is also a supply chain aspect. Communication and traceability between a wafer processing facility and a test and assembly house has become more important. Standards activity is taking place for chip traceability and for data transfer between facilities.
Factory automation
Automation will become pervasive in 300 mm fabs, in part for ergonomic reasons, but mainly for productivity reasons. There are ergonomic limits to how high 300 mm front opening unified pods (FOUPs) can be stacked and to how far they can be carried. Those limits can interfere with the layout needs and stocker capacity requirements for the fab.
Semiconductor manufacturing is no longer technology limited; it is productivity limited. Automation must be in place for consistent and predictable material movement. Also, the data handling requirements in a fab are increasing exponentially to meet yield management and process control needs. Those needs are reaching the point where the data handling infrastructure must be in place first, before the tools. Every piece of information from engineering lots is vital for process ramping. Also, the conflicting goals of continuous processing and reducing unscheduled downtime require more finely tuned execution control.
