Fast-Ramp Furnace Improves Solder Reflow Process

		At a Glance
	Today's solder bump reflow processes require uniform temperature control and total ambient control during ramp-up, processing and ramp-down procedures. New fast-ramp vertical furnaces provide a nearly oxygen-free environment, precise temperature uniformity, high wafer throughput and a lower cost-of-ownership than belt furnaces.

I n flip-chip packaging, the quality of the solder bump reflow step largely dictates packaging yield. The creation of uniform, hemispherical bumps relies on precise temperature and ambient control during reflow. In the furnace, it is imperative that the temperature profile be uniform and held within a very tight tolerance, wafer-to-wafer, wafer center to edge, for the entire batch load. A virtually oxygen-freeenvironment(<5 ppm) is required to minimize bump oxidation, en-suring high-quality adhesion of the bump to the substrate. We review the stringent requirements of solder reflow processes and compare cost-of-ownership (COO) of a fast-ramp vertical furnace vs. a traditional belt furnace.

The interconnecting scheme between the semiconductor chip and substrate becomes ever more complicated each day.¹ As more functions are integrated on each chip, as many as 500 interconnections to the printed circuit board can be required. With clock rates exceeding 300 MHz, chip packaging technology must address the need to control parasitic capacitance and induction paths, as well as heat generation, shrinking board space and thermal expansion matching issues. Flip-chip technology provides the shortest electrical path to other components, occupies the smallest area on the board and can be designed for excellent thermal conduction.

One of the earliest and most common flip-chip technologies is the C4 process (controlled collapse chip connect), first developed by IBM.² During this process, individual die with device side solder bumps are positioned on top of the carrier substrate solder pads. Then, the entire assembly is passed through a low-temperature oven to form a complete bond.

Solder bumping on the wafer, usually the last process performed on the wafer before sawing, must repeatably and reliably yield symmetrical half spheres of solder at each required interconnect interface. As shown in Figure 1, the process begins by depositing a glue layer, usually chromium (Cr), onto the aluminum contact pads. Then, a copper/ chromium layer is deposited, followed by a thin layer of gold (Au). A patterned lead/tin (Pb/Sn) solder is deposited either by evaporation or plating. The reflow process then requires heating of the wafer to a peak temperature range (350-400°C for Pb/Sn solder), staying within this range for a short time (2-10 min). Controlling the ambient during furnace ramp-up, processing and ramp-down prevents oxidation of the bumps, which impedes interfacial adherence of the bump to the substrate.

Equipment options 

Fig. 1. Ambient control during reflow prevents oxidation of the solder bumps, improving their adhesion to the package substrate.

Conventional batch diffusion furnaces provide a low COO process for solder bump reflow, yet they often do not have adequate response time at these low temperatures. Requirements for precise temperature control at the peak temperature may also not be met using these furnaces. Alternatively, lower-cost belt furnaces are capable of generating adequate temperature profiles for the process, yet require tradeoffs for implementation in manufacturing. Automation of these tools is difficult and expensive, throughput is typically limited to 20-25 wafers per hour and tool footprint is fairly large.

A small-batch, fast-ramp vertical furnace offers excellent response time at the low solder reflow temperatures and can process wafers in a more tightly controlled ambient. The furnace also occupies less than 15% of the space required for belt furnaces, while yielding productivity gains on the order of 100%. The tool used for this study is comprised of two vertical furnaces that share a wafer handling system, all housed within a single enclosure. Each furnace processes 50 wafers in a batch. Ramp-up rate for this process is typically 40°C/min, with ramp-down of 20°C/min.

Performance and COO

Fig. 2. Temperature profile for a typical Pb/Sn reflow process, which differs depending on the melting point of the solder.

In this vertical furnace, each process chamber has a process tube and a boat-holding baseplate. The process tube is raised and lowered along the same axis of the elevator. Wafers are loaded onto the boat, and the process tube is lowered to mate with the base-plate and to form a leak-tight chamber. The chamber is nitrogen purged to a desired atmosphere, followed by the introduction of either hydrogen or forming gas. An oxygen analyzer continuously monitors oxygen content, which must remain below 5 ppm. Next, the chamber is raised into the heating module, which is at a preset temperature. The furnace follows the prescribed temperature profile until the temperature reaches its preset value, measured using a thermocouple. After processing, the chamber is pulled out of the furnace module and lowered to the cooling area with a controlled ambient to achieve rapid ramp-down, while the heating chamber remains at the process temperature. Once the wafer temperature is lowenough(<50°C), the wafers are exposed to atmospheric ambient. Figure 2 shows a typical Pb/Sn solder process. For different solder materials, peak temperature and process times are programmed accordingly.

Table 1. Dual Fast-Ramp Vertical Furnace vs. Belt Furnaces
Technical results	Dual fast-ramp vertical furnace	Belt furnace
Oxide layer	<30 Å	>=100 Å
Temperature uniformity
Within the furnace	±1.0°C	±2.5°C
Within the wafer	±0.5°C	±2.5°C
Oxygen levels during process	<5 ppm	10 ppm
Economic results
Process gas requirements	2.5 slm	110 slm
Footprint	2 m2	7 m2
Throughput	60-80 wph	25-35 wph
COO	$2.72	$4.70

Numerous experiments confirm the accuracy and reliability of this furnace design for the reflow process. Nine-point thermocoupled wafers were run through the process to determine temperature uniformity within the wafer, wafer-to-wafer and within the furnace. Results indicate that within-wafer uniformity is within ±0.5°C, wafer-to-wafer uniformity is within ±1.0°C and temperature uniformity within the furnace is ±1.0°C.

A COO analysis comparing the dual fast-ramp vertical furnace with a belt furnace (Table 1) indicates significant savings with the vertical furnace for this application. Effective throughput is more than 60 wafers per hour. Combining the process capability and COO offered by this system, it is likely to become a tool-of-choice for next-generation solder bump reflow processes.

References

1. R. Prasad, "Technology Driven Component Package Trends," Semiconductor International, April 1996, p. 116.

2. L.F. Miller, IBM Journal of Research and Dev., Vol. 13, 1969, p. 239.

3. C. Lee, G.C. Noblitt, "Next Generation Challenges to Thermal Processing," Semiconductor International, March 1996, p. 73.