Wafer Level Packaging For CSPs

		At a Glance
	Low-density I/O devices can be packaged at the wafer level. Compression molding is used to apply and cure an encapsulant on a bumped wafer. After dicing and ball transcription, the devices are complete.

IC packaging has changed rapidly in the past two years, driven by design requirements for portable computing and mobile communications equipment. In 1996, chip scale packages (CSPs) emerged in the U.S market. In 1997, CSPs gained momentum by their rapid adoption in the flash memory market. Now, the CSP is poised to become a key semiconductor package type for consumer products.

According to the EIAJ/JEDEC definition, a CSP has a size that is only 1.2 times the original chip size. To be competitive, the pricing structure of a CSP should be in parity with the conventional package it replaces and use existing assembly infrastructures when possible. To date, more than 35 CSPs have been introduced since the concept was first presented by Junichi Kasai of Fujitsu and Gen. Murakami of Hitachi Cable (Tokyo, Japan) and demonstrated by Mitsubishi Electric (Tokyo, Japan). CSPs are being classified into four categories:

• Flex circuit/tape
• Rigid substrate
• Custom leadframe
• Wafer level package

The flex circuit type is defined as a tape-based substrate functioning as an interposer. An example of this CSP type is Fujitsu's fine-pitch BGA (FBGA), using flash devices for portable applications. The FBGA footprint, at 0.80 mm pitch or smaller, is similar to Tessera's (San Jose, Calif.) µBGA, but the FBGA's package construction follows that of a standard die attached, wirebonded, overmolded BGA. Other examples include Texas Instrument's (TI, Dallas, Texas) MicroStar and NEC's (Tokyo, Japan) FBGA.

The rigid substrate type is defined as a CSP using a ceramic or laminate substrate. Its construction is the same as a CBGA or PBGA, but it is much smaller in size and pitch, meeting the JEDEC/EIAJ CSP definition. An example of this package is the multichip CSP (MCP CSP), which is forecast to reach production in 1998 utilizing SRAM+ flash chips for cellular applications. It is designed and will be manufactured under a joint Fujitsu-Toshiba agreement. Other examples include Motorola's (Austin, Texas) JACS-PAC and SLICC.

The leadframe CSP type closely follows the construction and assembly process used in conventional package construction. For this CSP type, the limiting factor is based on the minimum manufacturing capability of the leadframe supplier in geometry definition and thickness. An example is Fujitsu's bump chip carrier (BCC) with PLL devices for wireless applications. Although the construction and assembly process is similar to that of a conventional package, the CSP technologies leveraged are the leadframe fabrication where the terminals are etched and the fine-pitch control needed for wirebonding. Other examples of leadframe CSPs are Mitsubishi Electric's molded CSP and Hitachi Cable's LOC.

Fig. 1. The Super CSP (SCSP) is an example of wafer level packaging. Except for solder ball transcription, all packaging is performed before dicing.

The fourth category, wafer level CSPs, suggests the possibility of an almost "package-less" finished product (Fig. 1). An example of this CSP is Fujitsu's Super CSP (SCSP). The package is basically constructed as an extension of the wafer fabrication process rather than a separate back-end assembly process.

A "real size" chip package

The SCSP is designed to reduce the package size to almost the size of the semiconductor device. It is also designed to cost a fraction of typical assembly cost, because packaging can be done before dicing. Encapsulation is done at the wafer level, on bumped wafers, using a new transfer molding technique. The result is a package only slightly larger than the chip itself.

The ideal requirements for a CSP include small size, fit with an existing infrastructure and low cost. A 48-pin SCSP is 9.0 x 4.5 x 1.0 mm at 0.75 mm BGA pitch. The encapsulant resin is 90 µm thick with the eutectic ball height at 0.40 mm. By way of comparison, the TSOP measures 18 x 12 x 1.1 mm. This translates into a mounting space and volume savings of more than 80%, because peripheral leads, wirebonds and leadframes are eliminated.

In addition to the small size and the use of proven infrastructure, investments to develop the package are minimal, with unit pricing targeted to be competitive with other CSPs. Cost factors for these packages include material and labor in both the front-end and back-end steps, while costing for the SCSP incorporates only front-end and a fraction of the back-end steps.

Another benefit of the package is that its structure allows flexibility in the type of low-density devices that can be packaged. Examples include flash, SRAM and other memory devices for portable applications like camcorders, cellular phones, digital cameras and notebooks. It has a BGA footprint, so I/O assignments can be standardized and made compatible with other BGAs or CSP types. Also, the BGA terminals allow for ease of board mounting using traditional surface mount technology (SMT) processes, without the need for an underfill.

The package can be used for either peripherally leaded or area array die. Peripheral pads of low density are redistributed to form an area array with a coarser pitch of 250 µm. Designers considering this package should pay attention to the added inductance associated with redistribution traces in high-frequency applications, while also understanding that minimized trace lengths improve performance. Also, the designer should consider the placement of the redistributed layer over active areas of the die and place the redistributed bond pads as close as possible to the original peripheral die pad.

Fig. 2. Encapsulant is applied at the wafer level by compression molding.

Fig. 3. After removal of the protective film, dicing is performed, and then solder balls are added to complete the device.

Also important are the wafer bumping characteristics. For example, bond pads sizes on the board and die should be scaled so that bump volume and height increase the fatigue life reliability of the solder joint. Optimizing the bump height allows better stress relief of thermal mismatches, better adjustment to planarity variation on the board and higher yields during attachment to the board. Pad size and placement should be designed to accommodate the pitch capability of wafer bumping  and stress areas of the die.

Because of the small size of the package, a potential limitation is the amount of power it can dissipate. One notable advantage is that the backside of the die faces outside and will assist in extricating heat out of the die. Nonetheless, the heat sinks/spreaders used must be small and light enough so they do not damage the die because of weight constraints or attachment methods.

Process flow

After the devices on the wafer are fabricated and redistribution is performed, the process begins with underlayer barrier metal (UBM) deposition. Titanium (Ti), the conductive layer, is first sputtered on top of the aluminum die bond pad. Next, nickel (Ni), the buffer layer, is sputtered on top of the Ti coating. Resist is then applied and patterned for the UBM, followed by etching and resist removal.

The second wafer bump phase is preparation for the plating processes. Resist is once again applied for the bump pattern, and barrier metal coatings of Ni and solder are applied. Resist is then removed, and Ti is etched away to complete the UBM structure. The bump pads are then reflowed.

After wafer bumping, the next stage is the compression mold process (Fig. 2). The mold apparatus consists of an upper and lower mold cavity, designed for the bumped wafer to be inserted in between. The lower mold, which is composed of board-like parts, has an opening to set the wafer and columnar parts to move the mold vertically. The encapsulant material comes in the form of a mold resin tablet, and it is centered on top of the wafer.

A temporary film is inserted between the upper mold and the resin tablet. This film allows the wafer to be released from the mold after the molding process, and it protects the bumps during the mold process. The tablet is a silica-filled, epoxy compound encapsulant. The material's coefficient of thermal expansion (CTE) is <30 ppm/&degreeC, with a viscosity of <120 poise and >160 cm spiral flow. The protective film is a thermoset with a Young's modulus of 2 Gpa at 200&degreeC and a surface roughness <0.3 µm.

Next, the mold compresses the encapsulant-covered wafer and heats it to 170&degreeC. At this point, the encapsulant is melted and flows across the entire wafer surface. It is important at this step to have a fluid encapsulant of a well-controlled volume. A suitable coating is thick enough to protect the wafer but thin enough to achieve portable equipment requirements. During this 5 min clamping step, the encapsulant hardens through post curing. Afterward, the wafer is released from the mold apparatus

The key technology for the package is compression molding of the encapsulant on a bumped wafer. The choice of thermosetting resin, the hardening speed of the resin and retaining consistent planarity are among the variables involved in optimizing the process.

After the wafer is removed from the mold apparatus, the protective film is peeled from the wafer surface. Material characteristics such as film elasticity and surface roughness are key parameters in the film's adhesion to the encapsulant and its removal without damage. The film also protects the bump pad areas so that a final cleaning step is not required. A dual blade is used to singulate the wafer into separate units. The process is completed by aligning solder balls to each of the exposed bumps. The balls are transcripted and reflowed, making the final product (Fig. 3).

To date, this package is more suitable for low-density lead counts. Investigation is ongoing to increase to higher density lead count capability. To do so, several areas must be examined to manage the mechanical stresses. One area is the UBM structure and its metallurgical effect on the die surface. Another area is the type of encapsulant used. It must have good adhesion with the die and contract at a rate that will not induce internal stresses. Also important is the bump pad/ball interface to the circuit board the SCSP will be mounted onto. Optimization of solder joint integrity and fatigue life are critical for application reliability. The recommended reliability testing criteria on a package level is similar to that of plastic BGAs.

Conclusion

With wafer level CSPs, like the SCSP, assembly becomes an extension of the wafer fabrication line rather than a separate line in the process. The only specific equipment required is the mold apparatus, in which different cavities are re-quired for wafer sizes but not different die types or sizes. They are smaller than conventional CSPs, and can be made at a fraction of the pricing since many assembly process steps are eliminated.