MCM-C Packaging Provides Cost Effective Multiprocessor Solution

		At a Glance
	Four 32-bit floating point DSP chips were integrated into a multichip ceramic cofire package to create a 480 MFLOP multiprocessor. Design and process development for ceramic quad flat pack (CQFP) and ceramic BGA (CBGA) packages are presented, explaining the implementation of thermoplastic adhesive and fine-pitch wirebonding to produce a high-yielding product.

Multichip modules (MCMs) for digital signal processor (DSP) applications have typically been fabricated using MCM-D (deposited dielectric) substrates. That was due, in part, to the pitch of the I/O bond pads on the chip and the requirements for routing the interconnect layers on the substrates. The electrical performance of the substrate was also a consideration, in particular, the inductance and dielectric constant (k) of the materials used in the multilayer structure of the MCM-D substrate.

More recently, improvements in the line, space and via diameter capability of cofired ceramic packages have enabled the realization of DSP MCMs in a cofired ceramic package (MCM-C). Use of cofire technology reduces the cost and assembly complexity of the module. New die attach materials have greatly enhanced the capability of rework, and along with a greater ability to fully test at probe, this has reduced the need for known good die (KGD). Improved fine-pitch gold wirebonding can be used in the MCM, enabling more dense designs than available with aluminum wirebonding on MCM-D substrates (Fig. 1).

Package design

The end use of the package must be taken into consideration when creating a package design. This application called for as small an outline and as thin a package as possible, while meeting MIL-STD-883 environmental screen as well as MIL-H-38354 qualification requirements. The package must have the ability to dissipate the power generated by the MCM, and it must be designed to maintain lead integrity during the assembly process, shipment to customer and board attachment.

Other environmental considerations are the ability of the package lid to withstand the pressure differentials of its end use applications, which could vary from near vacuum to several atmospheres of pressure, as well as temperature variations from 5°C to 125°C. Under low pressure, outward lid deflection must be limited to avoid shorting to a daughter board attached over it or to an adjacent PC board. Inward deflection under high pressure or low ambient temperature must be limited to avoid contact with the highest components or wirebonds.

The final body size of the package is limited by the number of I/Os and the pitch of the leads. There were 308 I/Os, and both 0.5 mm and 0.65 mm pitches were considered. The 0.65 mm pitch was chosen based on input from industry experts, who were reluctant about assembly pitches any finer than 0.65 mm on components with 250 leads or more. This led to a body size of 52 mm x 52 mm and a cavity size of 46 mm x 46 mm. A denser design was developed for the BGA version of the MCM.

Fig. 1. The SHARC multiprocessor module has four 32-bit floating point DSP chips that are integrated into a multichip ceramic cofire package.

Calculations for the 46 mm² cavity predicted a 0.3 mm deflection for a pressure differential of one atmosphere. An internal deflection up to 0.34 mm is expected when the lid compresses at very low ambient temperatures (5°C) because of coefficient of thermal expansion (CTE) mismatch. Accounting for these deflections led to an overall maximum package thickness of 4.06 mm when the maximum tolerances were considered. This ensured an internal minimum separation of 0.38 mm between the wirebonds and lid under maximum internal lid deflection. The DSP chips were recessed 0.3 mm into a cavity to achieve the overall thickness, as well as improve wirebond capability.

Bond pad design 

The bond pad spacing on the DSP chip is 153 µm. A fan out pattern for the substrate bond pads to increase the pitch is common, but it would have required too much real estate for this package. The bond pads were staggered (Fig. 2) to put them on the same pitch as on the chip. A via diameter of 100 µm was chosen to meet cofire design rules for center-to-center spacing of vias. The staggered pads also enabled the use of 153 µm wide bond pads, leaving increased area for placement of the second bond as well as adequate space for a rework bond. Some creative via placement would allow spacing as close as 100 µm, while still maintaining the cost advantage of the cofire technology. A similar approach¹ uses thin film, fine-line circuitry on a ceramic base.

One concern for using gold bond wires on a staggered design is wire skip. This occurs when wire extrudes out under the side of the transducer and comes unacceptably close to adjacent wires. This occurs primarily when the wire exits the capillary orthogonal to the transducer. To eliminate this, the package was bonded so that the wire exited at a 45° angle to the transducer. This also allowed the bonding parameters to be adjusted for optimum performance. Other machine features were also used to eliminate wire skip.

Fig. 2. A staggered bond pad pattern is used on the substrate to match the spacing on the chip and to save space.

Fig. 3. Wires bonded to the outer bond pad row are shaped with higher loops to increase separation and improve reliability.

Since the die is recessed in a 0.3 mm cavity, the loop heights were lower and the bond lengths were shorter than otherwise possible. The two layers that make up the cavity were also used as escape channeling layers for subsequent routing.

The loop of the wires was contoured to increase separation of the wires. The longer bond wires had higher loops than the short wires, resulting in a diagonal bond wire separation greater than otherwise achievable (Fig. 3). This approach also reduces the likelihood of wires shorting during vibration.

Another manufacturing enhancement is to provide a one-to-one correspondence between die and substrate bond pads, regardless of the presence of no-contact pads. This simplifies inspection of the bonds.

Die attach

The die attach material chosen for this module is a silver-filled thermoplastic material. A paste of the material was used for the capacitors and resistors, and a preform was used for the DSP chips. The thermoplastic material provides a number of distinct advantages. The silver-filled preform has good thermal conduction, with a thermal conductivity of 3 W/m°C. Since the thermoplastic process for capacitor attachment involves deposition and fusing of the paste off-line, the risk of shorting between terminals is eliminated.

Since the thermoplastic softens at the same temperature as the attachment temperature, elevated temperatures are not required to perform rework on the DSP die. The adhesive is also stable enough at wirebonding temperatures to prevent a die from "swimming." It also has lower stress than most thermoset epoxies, which is very useful for handling the CTE mismatch between the ceramic substrate and a large silicon die.

Current thermoset epoxies do not soften sufficiently to remove a die as large as the DSP chip used here until temperatures near 300°C are reached. Even at 300°C, significant shear forces must be applied to dislodge the chip. Application of the dislodging force itself can sometimes cause additional damage to the module. Cleanup of the pad for replacement epoxy is also difficult.

The thermoplastic adhesive allows the die to be removed with only a light force. Cleanup of the pad is accomplished very easily, resulting in a very smooth pad for subsequent replacement of the die. The shear strength achieved by the thermoplastic material at room temperature is two to three times that obtainable with thermoset epoxies currently used. This shear strength is particularly impressive for the capacitors where bond strength can be achieved without risking shorts.

Thermal considerations

Surveys of potential customers during the product definition cycle showed that the majority of customers would be using a printed circuit board with an internal core for cooling. Therefore, much of the heat produced would be transferred through the package base to the board. The 5 V version of the DSP module produces a maximum of 17.5 W with 7.2 W typical. The 3.3 V version produces 7.1 W maximum and 3.2 W typical. Early thermal modeling, based on a 2.54 mm base thickness, predicted a temperature rise of 1.3°C/W for a single die. The actual base thickness is 1.5 mm. For four die, this results in a predicted junction to case thermal resistance (q_JC) of 0.35°C/W at maximum power dissipation.

Thermal mock-up samples were assembled and infrared measurements were taken to verify the calculations. The measurement confirmed the predicted q_JC. The thermal mock-up units were constructed using a cofired, 0.060 in. thick substrate without leads. The substrate had a wirebond and die attach pad metalization on the top with no internal circuitry. The DSP chips were attached to the substrate, and the assembly was then spray painted flat black to control the emissivity. The assembly was attached chip-side down onto an aluminum plate. The assembly was placed on a hot plate, so that the aluminum plate conducted heat from the hot plate to the DSP chips. The hot plate temperature was varied and monitored using a thermocouple. The temperatures of the aluminum plate and the ceramic substrate above the die were measured using an IR camera.

The temperature of the aluminum plate was equated to the junction temperature of the DSP chip, and the temperature of the ceramic substrate was equated to the case temperature to obtain q_JC. Though experiments with actual devices were required to draw any real conclusions, this experiment did serve to validate the package thermal model.

Electrical considerations

The design goal for the multiprocessor MCM was 40 MHz operation. Cross talk, ground bounce and propagation delays are the main concerns at this speed. Layout considerations were made to minimize their adverse effects. The KGD issue was also considered.

To minimize cross talk, critical signal paths were determined early in the design phase, and lines sensitive to cross talk were separated and spaced appropriately. The thickness of the ceramic and the distance to ground and voltage planes were designed to provide 50 W transmission.

The worst-case scenario for ground bounce was assumed to be a write operation in which 86 signals simultaneously switch from high to low.² The effective ground pin inductance was assumed to be 7 nH, which for 28 ground pins gave an effective inductance (L_eff) of 0.25 nH. Typical output fall times as a function of load were used for the ground bounce calculations. The presence of ground planes and lower lead inductance in the MCM module combine to produce a predicted ground bounce for the MCM module that is lower than that of the single-chip package (Table 1).

To minimize propagation delay, the clock-in signal is brought to the center of the package and branched to the DSP chips. The propagation delay, with a relative k of 10, is 269 ps/in. Layout and routing were performed to match the delays within 30 ps. The round-trip propagation delay through branch stubs is <540 ps. This was less than the rise time of the signal, and it is considered satisfactory.

The KGD path was not pursued for this module. Tests were performed at 85°C at the wafer level. This approach is the least costly method and is the most economical method presently available. Though the yield is considered to be high enough to make rework unnecessary, the die attach process was designed to enable rework as a contingency.

Die attach process and equipment

Optimization of the assembly process and equipment starts with die attach. It has to be robust enough for the final assembly to survive environmental extremes, yet allow ease of rework. This is no small task with a die that is 15.66 x 16.09 mm in size. The adhesive material must provide good thermal conductivity and an essentially void-free bondline in order to dissipate the heat generated at peak duty cycles of the chip. The only material examined that met all requirements was a thermoplastic adhesive.

Thermoplastic adhesives offer superior adhesive strengths when compared to thermoset epoxies. They can easily be reworked at the same temperature that die attach is performed. The material cleans up very well from the die attach pad, providing for a smooth surface for reattachment of the die. The bond line is essentially void-free if uniform pressure is applied to the die surface during the attachment process. Also, the material requires no curing by design. It is essentially a hot melt adhesive, so there is no curing shrinkage to create interbondline voids.

The paste is available in a screen-printable formulation, and future plans call for screen printing of the material onto the back of the wafer prior to dicing. This will reduce handling of individual preforms at the die attach operation.

Thermoplastic adhesives form their adhesion by application of pressure at an elevated temperature for a few seconds. Pressure, temperature and time are interdependent parameters, and an optimization had to be established. The risk of die surface damaged because of applied pressure was evaluated at pressures in excess of that required for a good bond. The die were inspected before and after the application of pressure, and no damage was found.

To form a void-free bondline, the tool used to apply pressure to the die must cover at least 75% of the die surface. Otherwise, the die will flex, and the pressure applied to the adhesive will be nonuniform. This is more critical for larger die than for smaller die.

Availability of equipment to process the thermoplastic was the only shortcoming of the material. The process requires pressures in excess of that needed to perform eutectic attachment, so a custom process was developed on an automatic die attach machine. The hardware modifications required were slight. 

Wirebonding process and equipment

While finer pitches than the one used here are being bonded today in other style packages, a 153 µm pitch with vias is pushing the state-of-the-art for multilayer cofired ceramic technology. The wirebonder used contributed significantly to the success of the manufacturing results. The ability to contour the wire greatly enhanced reliability by allowing the separation between adjacent wires to be maximized. A bottleneck tool was used, and the inner row of package bond pads was bonded first. When the outer row was bonded, the loops were made higher and contoured into an approximate box shape  (Fig. 3). This provides for maximum separation and rigidity of the wire through out the life of the module.

In addition to the 45° bonding orientation, the machine was equipped with a dereeler to keep the wire from developing torsional stress. Removing torsional stress in the wire reduced the probability of wire skip. The combination of the 45° presentation and the dereeler eliminated the wire skip problem entirely.

Fig. 4. A typical plot of the ADRCLK signal from one of the DSP chips shows rise and fall times less than 1.5 ns. The total time shown is 50 ns.

Achieved performance

The design goal was to produce an MCM floating point multiprocessor that would represent the more cost-effective solution in terms of cost per MFLOP per unit volume. An MCM package would enable the floating point multiprocessor to be more competitive with fixed point processors, and thus open up new markets.³ The size advantages and reduction of system level cost of an MCM have been widely promoted, though more often than not MCMs have had a significantly higher component cost than discretes. This design has addressed the component cost element with efforts to make the MCM be more competitive both in initial component cost and in system level cost.

The component level cost has been addressed by designing the MCM to be highly manufacturable. First, using cofired ceramic technology for the interconnects rather than MCM-D substrates reduces the cost. The cost is further reduced by integrating the interconnect into the final package rather than having a separate interconnect substrate and a discrete package. Pushing the state-of-the-art in cofired technology without sacrifice of yield enabled the overall package outline to be kept smaller than otherwise achievable. Die attach and wirebonding processes were developed to produce a high yielding state-of-the-art process that further reduced the manufacturing cost. Enhancing the rework process rather than using the KGD approach also helped to contain cost.

Fig. 5. An X-ray shows a typical die attach bondline using the thermoplastic adhesive.

Using the above cost enhancements, the MCM can be produced at only a minimal increase in cost over the discretes. At the system level, cost analysis reveals the MCM approach offers at least a 20% lower cost.³ In terms of cost per MFLOP per unit volume, the MCM offers a 10x improvement.

The thermal performance of the package was evaluated using infrared thermography. The case temperature in still air was 76.8°C, and the die surface temperature was 78.8°C. The 2°C temperature difference for the MCM operating at 5.63 W yields a q_JC of 0.36°C/W, closely matching the model prediction.

The package passed all environmental tests. At 125°C, the lid deflection was 0.1 mm. In a partial vacuum (406 Torr), outward lid deflection was 0.42 mm, which is greater than the design value. While this does not create any functional problems, means of reducing the deflection are under evaluation.

The electrical performance met all design expectations. Ground bounce was measured to be half the predicted value for the ceramic quad flat pack (CQFP) version. The signal integrity was found to be clean, monotonic and coincident as required for proper functionality. Figure 4 shows the signal integrity for a ADRCLK signal for one of the die in the ceramic ball-grid array (CBGA) module. Similar results were obtained for the CQFP package.

The thermoplastic adhesive was qualified to MIL-STD-883, Method 5011. Acoustic microscopy and X-rays were used to find voids in the bondline. Figure 5 shows an X-ray of the bondline. Both the CQFP and the CBGA devices have passed qualification.

BGA version

A CBGA package for the Quad SHARC has been designed and qualified. The BGA version is 47 mm², reducing the footprint 30% compared to the CQFP version. The shorter I/O traces have led to improved performance. The ground bounce is predicted to be five times better than in the CQFP (Table 1).

The BGA design concentrates the I/O to a 25 mm square area in the center of the package. This enables the reliability of the package to be near that of a 25 mm package when attached to a PC board. Copper ball standoffs are placed at the corners to avoid solder ball collapse and enhance solder ball reliability.

Conclusion

A cost-effective MCM solution is achieved by designing the module for manufacturability by anticipating problem areas and developing processes or features in the package to address those areas. Use of proven technology pushed to "state-of-the-art" performance, but not to the point of diminishing returns, helped control cost while reducing size and enhancing performance.

Acknowledgments

I want to acknowledge Dale Smitherman, Glenn Romano, Ed Bradshaw and all the

Quad SHARC Development Team for their help. I also want to thank Jeff Bunch of the University of Limerick for consultation on thermal analysis.

This article has been adapted from a paper presented at the Pan Pacific Microelectronics Symposium in Maui, Hawaii, January 1997.

References

1. M.E. Williams, et al., "Enabling Fine-Pitch Wire Bonding Through the Use of Thin Film Metal On Ceramic," Proceedings of the International Symposium On Microelectronics, Los Angeles, Calif., Oct. 24-26, 1995.

2. H.W. Johnson, M. Graham, "High Speed Digital Design," p. 67, Prentice Hall, 1993.

3. R.K. Scannell, "A 480 MFLOP MCM Based on the SHARC DSP Chip, Breaks the MCM Cost Barrier," Proceedings International Symposium on Multichip Modules, Denver, Colo., April 17-19, 1996.