Improving Performance with Oxynitride Gate Dielectrics

		At a Glance
	The initial use of oxynitride as gate material for MOS VLSI applications has shown clear advantages in electrical properties and hot-carrier reliability vs. SiO2 gates. Optimized process conditions and the use of nitrogen sources allow for the formation of ultrathin gates where it is possible to localize the nitrogen at both the poly/SiO2 and the SiO2 /Si interfaces.

The size reduction in MOS device circuitry dictated by advancing technology through the demands of the SIA Roadmap requires the use of thin gate dielectrics with high performance and reliability. The dielectric material used in fabrication of the gate is a key factor in determining the long-term reliability of the device. In a MOS transistor, the gate dielectric must sustain a substantial voltage difference applied between the gate electrode and the underlying silicon substrate. In the realm of very-large-scale-integration (VLSI) circuitry, the gate length can be below 0.25 µm (250 nm) and its thickness below 100 Å. With such small dimensions, electrons can tunnel in the gate material when the device is toggled between on and off positions, in normal usage. The electrons can create the undesirable long-term effect of threshold voltage drift of the transistor, and eventually this shift could cause circuit failure by rendering the transistor incapable of switching states.

This problematic electrical reliability behavior can be a limiting factor for thermally grown SiO₂ gates with thickness in the range below 80-100 Å (8-10 nm).

This has been demonstrated¹ by the fact that while the injected charge-to-breakdown (Q_bd) for positive gate bias (+V_g) increases with decreasing oxide thickness, Q_bd for negative bias (-V_g) degrades rapidly (Fig. 1). This effect was attributed² to structural imperfections in the interfacial Si/SiO₂ region, where the stereochemical differences between SiO₂ and Si create high stress/strain in the transition layer.

To alleviate this stress, it was proposed to introduce a small quantity of nitrogen (N) in this transitional region that would reduce the number of distorted Si-O bonds and therefore improve the observed Q_bd (-V_g) behavior. In fact, the formation of oxynitrides at the interfacial region clearly improves the electrical behavior for Q_bd (-V_g) while also improving the Q_bd (+V_g). This results in a higher Q_bd (+V_g) than obtained for "pure" SiO₂ of similar thickness (Fig. 2).

In addition, another important advantage obtained by the introduction of N at the Si/SiO₂ interface is that it behaves as a barrier to boron atoms, impeding their penetration into the gate material, which is typically observed when p⁺ polysilicon is used in p-MOSFETs. ³ A more detailed discussion on the effects of this migration is reported later in this article.

Gate nitridation

Fig. 1. Oxide thickness dependence of Qbd under the same stress current for both gate polarities.

Several techniques have been used for the formation of oxynitrides. Depending on the N source used, these can be grouped into three categories: NH₃, N₂O and NO. The use of NH₃ is advantageous⁴ in introducing large amounts of N at the Si/SiO₂ interface, and thereby producing the highest boron stopping scenario. However, the presence of hydrogen produces the unwanted effect of electron trapping, which introduces a severe limitation effect to this methodology.⁵  

Introducing N₂O in the oxidation chamber produces very high-quality gate oxides, showing im-proved electrical properties (Fig. 3)⁶. The kinetics of this process has been shown to be highly dependent on temperature, pressure and furnace geometry.⁷ Prior work data indicate that NO (produced by thermal dissociation of N₂O) is the species responsible for introduction of N into the oxide.⁷ The limitation often found with this N source is that the amount introduced is not very high, and consequently, the boron-stopping effect is reduced. Chemical analysis (AES, XPS and SIMS) demonstrates that amounts from 1% to 5% of N can be introduced by using N₂O. ⁸ In contrast, a definite advantage of N₂O usage is the low thermal budget required to obtain an oxide of desired thickness in adequate processing times.

This lowering of thermal budget represents a desirable processing advantage. NO-grown oxides require even lower thermal budgets than those used in N₂O processing, to introduce the same quantity of N into the gate oxynitride. In addition, NO-grown oxides also exhibit a higher amount of N incorporation than is the case with N₂O, at similar processing conditions. This higher amount of incorporation is probably the consequence of completely different growth kinetics, as demonstrated by the much slower growth rate of the oxynitride layer in a NO ambient, as compared with N₂O. It is postulated that the higher amount of N introduced at the Si/SiO₂ layer has a retarding effect on the growth of the oxide itself, as is thus the limiting factor.⁸ Excellent electrical properties are demonstrated by the NO-grown gates, confirming the importance of N introduction into the SiO₂ gate material and at the interface.⁸

Gate performance

Fig. 3. Effective mobility vs. effective electric field for MOSFETs with SiO2 and N2O oxides.

Such improvement in electrical properties manifests itself in a higher flat band voltage (V_fb) stability in p⁺ polysilicon gated p-MOS capacitors. The use of p⁺ polysilicon in CMOS p-channel circuitry is needed to improve short-channel performance.⁹ However, boron diffusion from the heavily doped p⁺ poly through the thin gate dielectric into the base channel region can cause undesirable drastic degradation effects in the circuit. As mentioned previously, the N introduced at the Si/SiO₂ interface by using a NO atmosphere during oxidation can effectively create a barrier to such boron penetration. The advantage obtained by N accumulation in the interfacial region is somewhat mitigated by a decrease in gate reliability because of the accumulation of boron within the gate itself. ¹⁰ This effect is schematically illustrated in Figure 4, which shows the effect of the oxynitride interface layer in stopping boron penetration and producing an accumulation of boron atoms within the gate. Such accumulation results in degradation of the gate charge trapping properties, as confirmed by charge trapping studies. ¹⁰ 

Fig. 4. The effect of the oxynitride interface layer (bottom) is compared to a gate without such a layer (top). The oxynitride layer stops boron penetration and produces an accumulation of boron atoms within the gate.

However, while such degradation is certainly an undesired effect, the overall performance and reliability behavior of NO-grown gate dielectric material is always superior to a control SiO₂ gate sample of similar thickness obtained by classical methods.

Optimal N distribution

Through the studies mentioned above, it was also observed that different process conditions and/or N source gases can introduce N at different positions within the gate itself, relative to the poly electrode and the underlying base channel layer.⁸ This leads to trying to position the N atoms within the gate to optimize both electrical and reliability performance.

To achieve different N distributions within the gate, different process conditions were employed, as well as different gaseous sources of N. ¹¹ Most notably, three different N profiles were generated and confirmed by SIMS within a p⁺ poly PMOS device with a gate thickness of about 50 Å:

• Case A: N peak located at the SiO₂/Si interface, generated by growing oxide in pure O₂ ambient, followed by a short NO anneal
• Case B: N peak at the poly/SiO₂ interface, generated by N implantation, followed by N₂ anneal (30 min at 900°C) to drive in the N at the desired interface
• Case C: N peaks at both interfaces, generated by a combination of the two methods mentioned above

These three profiles were compared with a control sample with SiO₂ gate of the same thickness. The boron trapping behavior of these three cases is shown in Figure 5.

In all three cases, electrical properties are improved as demonstrated by suppression of V_fb shift because of the presence of the boron barrier, regardless of its position within the gate area.

In addition, interfacial properties are also significantly improved, as demonstrated by reduction of the initial interface state density (D _it).¹¹ However, when a minimum amount of boron does penetrate into the gate, as is the case when high drive in temperatures are employed (950°C), undesirable states of interface density are created, resulting in high D_it, which could lead to degraded performance during electrical stress.

When considering the effect of the N peak position on improvement of Q _bd (-V_g) behavior vs. the control SiO₂ sample, another tradeoff appears. Positioning the N barrier at the poly/Si interface (Fig. 5b) improves the Q_bd characteristics, while the effect is contrary for Case A, where Q_bd performance is decreased. Case C appears to be somewhat in the middle of the two previous cases, demonstrating only a slight advantage vs. the control sample and a slight degradation vs. the best behavior as shown by Case B. It is also interesting to note that this variability in Q_bd behavior under negative stress (-V_g) does not appear in the case of n-MOS devices, where all three cases show similar performance (this could be rationalized as these are majority carriers going to minority and little compensation occurs).

This performance behavior of the three cases can be explained by considering the four cases exemplified in Figure 5: 

Fig. 5. The impact on boron penetration of gates (a) without any interface layers, (b) with nitrogen at the SiO2/Si interface, (c) nitrogen at the poly/SiO2 interface and (d) nitrogen at both interfaces.

• Figure 5a represents the control, where boron can diffuse easily into the gate during activation, resulting in degradation of interface quality and reliability.
• Figure 5b shows the blocking effect of an N barrier at the SiO₂ /Si interface, which does reduce V_fb shift, but accumulation of boron atoms within the gate causes charge trapping, provoking Q_bd degradation.
• Figure 5c shows an improved scenario, where the N barrier positioned at the poly/Si interface greatly decreases boron penetration into the gate oxide, resulting in improved Q_bd.
• Finally, Figure 5d portraits the behavior in the presence of the "double wall" N barrier. This renders impossible for boron atoms, which penetrated the first barrier (at the poly/Si interface) to penetrate into the gate, yielding the smallest V_fb shift. However, boron atoms within the gate are now effectively "trapped," leading to decreased Q_bd performance when compared with the case presented in Figure 5c. In this case, Q_bd performance is better than the cases of Figures 5a and 5b, as much less boron can penetrate the gate because of the presence of two blocking "walls."

Recent developments

An alternative methodology for the formation of a N barrier at the poly/Si interface has been recently patented.¹² In this process sequence, a mixture of NO and N₂O gases is employed, yielding a peak N concentration of about 7%. This produces a case similar to the one presented in Figure 5c, however the overall thermal budget has been decreased vs. the methodology practiced previously, where a long anneal (30 min at 900°C) is needed. As a result, much less boron does penetrate the gate, improving charge-trapping characteristics. Current research efforts are directed toward defining a simple process sequence where the "double-wall" N distribution presented above is obtained more simply by changing the ratio of the NO/N₂O mixture in the reaction chamber. It is speculated that the lower thermal budget required by this process could generate an optimal circuit where the drawback of reduced Q_bd performance described above for Figure 5d is avoided.

Conclusion

Different process sequences and various gaseous N sources allow one to "engineer" N profiles within an oxynitride gate, leading to improved performance and reliability. Current and next generations of MOS devices can benefit from this technology, in particular dual-gate CMOS designs, by means of improved performance and reliability.

Acknowledgments

This research was conducted at the University of Texas at Austin, Microelectronics Research Center. All gases used in this work were donated by Scott Semiconductor Gases, a division of Scott Specialty Gases Inc.

The authors gratefully acknowledge the wisdom and knowledge of Dr. William Kroll of Emcore Corp., who provided great insight and help in the final preparation of the manuscript.

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