The Challenges of 300 mm Wafer Cleaning

		At a Glance
	Wet batch cleaning has continued to meet most of the cleaning and stripping requirements through 250 nm manufacturing on 200 mm wafers and has demonstrated successes at 180 nm geometries on 300 mm wafers. This article identifies and explores solutions to anticipated challenges as the industry moves to sub-180 nm geometries, where late in this era, >90% yields on 130 nm and 100 nm devices will be required.

Traditional aqueous-based chemistries can achieve the particle, metal, roughness and oxide etch uniformity requirements for pre-gate cleans predicted in the SIA roadmap. The difficulty occurs in scaling current batch wet technologies while integrating to the preceding and succeeding processes and simultaneously reducing the environmental impact, improving safety and reducing cost of ownership for each process. Scaling will be-come even more difficult late in the 300 mm era when >90% yields on 130 nm and 100 nm devices will be required.

Though alternatives to batch wet cleaning have been available to the industry for several years, the move to 180 nm devices and 300 mm wafers will likely make them necessary to meet key challenges not achievable by current batch wet processes. Projected process requirements for 300 mm wafers for various device generations and roadmaps are shown in Table 1.^1-3 Predictions as to a technology's scalability can be made on a metric-by-metric basis by examining the mechanisms that are involved in the process.

Particle addition

Reducing the number of contaminants requires minimizing the number of particles added per wafer pass (PWP) and maximizing particle removal. The sharp decrease in the allowable PWP for 300 mm pre-gate cleans constitutes the single greatest challenge in cleaning. As the critical defect size drops 60% from 125 nm to 50 nm, allowable PWP decreases by an order of magnitude (Table 2).

Estimates of compliance to 250 nm Unified Specification can be determined by scaling the results for wafer and particle sizes since the current quality of 300 mm wafers does not permit testing in the required ranges. Figure 1 shows the particle performance of a centrifugal spray processor on 200 mm wafers measured at 0.15 µm. The mean addition of 1.24 particles scaled to the area of 300 mm wafers (2.3X) and to 0.12 µm particles (1.56X) is 4.5 PWP. This meets the 1998 60% yield requirement for 250 nm and nearly meets the 80% yield requirement. Such tests are very useful for the initial phases of process optimization. There is, however, a legitimate concern as to the validity of these scaling factors. Particle addition testing and process development on 300 mm wafers at the specified particle sizes need to occur as soon as suitable wafers and particle counters are available.

Particle counting metrology is also a serious issue. The first generation of 300 mm particle counters specifies 95% detection of 0.08 µm latex spheres. The extension of current optical, particle-counting technology to 0.05 µm should be possible with more powerful, shorter wavelength lasers focused to smaller spot sizes.

Particle removal

At 100 nm device geometries and 95% yield, less than one particle added per 10 wafers is allowable. Achieving these addition levels will likely require efficient removal of pre-existing particles.

Contaminant removal is a two-step process. The contaminant must first be detached from the surface and then be rinsed away. In the case of particles, detachment in a batch wet system can be accomplished by a partial undercut in conjunction with megasonic energy or an undercut alone.

Table 2. Particle Addition Limits
Generation	Particle Size	60% Yield	80% Yield	90% Yield	95% Yield
250 nm	125 nm	9.6	3.9	1.8	0.86
180 nm	90 nm	4.8	1.95	0.9	0.43
130 nm	65 nm	2.24	0.91	0.42	0.20
100 nm	50 nm	0.96	0.39	0.18	0.086

The partial undercut of particles by an etchant, such as SC-1, combined with megasonic energy has served well for particle detachment for over 20 years. This approach will likely meet the 180 nm requirements of 95% removal at 0.09 µm. However, the megasonic removal force drops as the inverse cube of particle diameter, while the adhesion force only drops as the inverse of particle diameter. Thus, small particles are removed less effectively than large ones.⁴ Fortunately, the force on small particles rises with increasing megasonic frequency. While technically challenging, increasing the megasonic frequency should permit the removal of sub-0.1 µm particles.

For 300 mm wafers, the sharp decrease in the minimum number of allowed particles added per wafer pass for pre-gate cleans constitutes the single greatest challenge in cleaning.

Undercutting the particles allows high particle detachment efficiencies without the use of megasonic energy if a highly efficient rinse is present. Figure 2 shows over 99% removal efficiency of Si₃N ₄ particles is achieved in a centrifugal spray processor when using either SC-1 or dilute HF (DHF) as an etchant.^{5, 6} As small particles are undercut more easily than large ones, this detachment mechanism is likely to scale well with decreasing particle size through the 300 mm era.

After detachment, particles must be transported out of the system. If not quickly rinsed away, particles can redeposit. Ineffective rinsing creates cross contamination within a wafer and between wafers. In overflow rinsing, the bulk of the water passes between the wafers, far from the wafer surface. Megasonic rinsing improves the efficiency of an overflow rinser by creating mixing in the bath through streaming. Although it is water-intensive, megasonic rinsing is likely to satisfy the rinsing performance requirements of 180 nm technology.

The rinse process would be much more efficient if water only passed near the surfaces of the wafers where the contaminants are located. This, along with the use of centrifugal force to spin off contaminated liquids, is the basis of ramped rinsing.⁷ A thin layer of water is sprayed on the wafers, and the contaminants are allowed to diffuse into the liquid. Of the contaminated water, >99% is subsequently spun off with centrifugal force. The process is then repeated with a greater than 100-fold reduction in contaminants per cycle. Ramped rinsing uses less than 1/10 the water as megasonic rinsing. This technique scales well with increasing wafer size and can provide effective rinsing throughout the 300 mm era.

Metal addition

Fig. 1. Trends in the number of particles added and removed is indicated for 33 runs of six 200 mm wafers using current batch wet processing.

For a given liquid chemistry, metal contamination typically scales linearly with the chemistry's metal content. Surface metallics after an SC-1, SC-2 process with fresh 30-100 ppb per metal grade chemicals are already in range of 1310¹⁰ at/cm².

Routinely reaching 10⁹ Atoms/cm² metals levels necessary for the 300 mm era however, will require "smart chemistries." For example, metal deposition from DHF can be suppressed through the addition of sub-percent levels of HCl or H₂O₂ to the mixture.⁸ Similarly, deposition from SC-1 can be reduced through the use of chelating agents to bind the metals in solution, ⁹ and deposition from the rinse water can be eliminated by slight acidification.¹⁰ No significant improvement in water or chemical metallic levels is therefore likely to be needed at 300 mm if such chemistries are implemented.

Metal removal

Fig. 2. Trends of Si3N4 particle removal are indicated for 33 runs of six 200 mm wafers using current batch wet technology.

The equilibrium between the metal deposited on the surface and dissolved in an SC-2 solution, favors the dissolved species very strongly . Virtually all surface metalics can be removed to 100 nm levels by SC-2 or DHF with an oxidant. This is illustrated in Figure 3 where the removal of metals deposited from a metal-spiked SC-1 solution is comparable for both standard and "dilute" SC-x chemistries.

The one notable exception is nickel deposited on bare silicon, which appears to spontaneously form nickel silicide compounds at room temperature. These compounds are quite insoluble and currently must be undercut to be removed. Cleaning chemistries must be formulated, either through extreme purity or smart chemistry, to minimize nickel contamination to the hydrophobic silicon.

A requirement for rapid removal by SC-2 is that the metals be present on the surface, not embedded in a film. For instance, aluminum or sodium that is buried in a chemical oxide during an SC-1 exposure must first be leached from the oxide prior to a slow removal by SC-2. These contaminants can be removed quickly with a slight etch of the oxide, but it would be far better if incorporation were avoided through the use of extreme purity or smart chemistries.

Etch uniformity

Fig. 3. Metal removal performance of dilute and standard RCA concentrations in various cleaning processes are comparable to the TXRF detection limit.

Some process attributes such as metals addition and removal are the result of local chemical equilibria and should not be affected by increased wafer size. Etch uniformity however, is a global phenomenon controlled by the mass transfer of etchants and rinse water. The larger the area of the wafer, the more difficult it is to precisely match the etchant concentration profile across the surface during the etch. Further, the SiO₂ etch requirements are very tight, 1.66% (1 s) for all variations combined (cross-wafer, wafer-to-wafer and run-to-run) in the 250 nm Unified Specification. No system currently in production consistently meets this requirement on 300 mm wafers, even with a blanket, unpatterned oxide.

There are also physics issues associated with these levels of etch uniformity. For example, 1.66% (1s) uniformity on a 3.5 nm gate of a 180 nm device requires ±0.05 nm (;1/4 the size of an SiO₂ molecule) measurement and control. Current "sub-atomic" measurements average thickness of a film over hundreds of square microns. Electrical breakdown of a 3.5 nm thick film however, occurs due to local nanometer-scale variations in the films.

The increase in wafer size has been a particular problem with traditional immersion systems. To optimize the mass transfer and achieve good cross-wafer uniformity, an immersion system requires very rapid insertion of the wafers into the etch and rinse baths. The increased velocity required by 300 mm wafers creates difficulties with bath splashing and wafers "floating" up from the carrier during insertion. The hydrophobic areas on a patterned wafer are likely to cause cross-die variations in oxide etch rates due to variations in local (sub-millimeter scale) exhaustion of the etchant and by perturbing the distribution of etchant across the surface of the die during transfer from the etch to the rinse bath. These effects can be reduced by long etches in very DHF, but at the expense of throughput.

Figure 4 shows the oxide etch performance of a centrifugal spray processor on 300 mm wafers at the I300I program. The system demonstrated a 2.4% (1s) total non-uniformity, which can be broken down into 2.17%, 0.76% and 0.60% non-uniformity due to site-to-site, wafer-to-wafer and run-to-run, respectively. Meeting the 1.66% (1s) total non-uniformity specification should be possible with tighter temperature and concentration control of the chemicals.

Surface roughness

Fig. 4. Average oxide removal on 300 mm wafers monitoring three positions in a cassette show a 2.4% 1s total etch nonuniformity over all points in 31 runs.

Current 200 mm and preliminary 300 mm data indicate that increases in roughness of less than 0.02 nm RMS can occur in HF-RCA and HF-DI:O3 cleans.⁵ The current 100 nm generation goal of 0.1 nm RMS seems generous and may need to be adjusted when more data on 1.5 to 3 nm equivalent oxide thickness gates are available.

One potential source of roughening involves the interaction of wafer diameter and process carrier pitch when achieving high particle removal efficiencies with megasonic agitation. Throughput and reduced bath volume in immersion systems are usually achieved by combining the wafers from two or four transfer boats into one process boat. This results in half- or quarter-spaced wafers with a wafer pitch of 5 or 2.5 mm and an inter-wafer spacing of 4.2 or 1.7 mm. The longitudinal waves from a megasonic transducer operating at 850 kHz have a wavelength of 1.8 mm. The energy in the waves is damped substantially when passing through the gap between half-space wafers and even more so between the 1.7 mm gap of quarter-spaced wafers. This damping can be compensated and the center of the wafers cleaned by increasing the power density of the megasonic energy. This increase, however, is at the risk of inducing excessive cavitation and wafer damage near the edges of the wafer. ¹¹ If available, high-frequency megasonics should reduce the severity of this effect.

Alternatives

Alternatives to batch wet cleaning include brush scrubbers, single-wafer wet spinners, single-wafer vapor processors, single-wafer dry processors and batch vapor processors. While these technologies have been available to the industry for several years, they have not been widely utilized, because batch wet process technologies have continued to meet most of the cleaning and stripping requirements through 200 mm, 250 nm production. With each technology node advancement however, certain cleaning, etching and stripping applications have developed that require process capabilities beyond batch wet cleaning. The move to 300 mm wafers may also provide additional key opportunities for these alternatives.

Currently, the only alternative cleaning and stripping processes that are specified in I300I or SELETE documents are for resist ashing (single wafer dry)^{1,2, 12}, post-CMP oxide cleaning (brush scrubbing)¹ and chemical dry etch (CDE) nitride stripping (single wafer dry). ¹² Other applications that currently use alternative cleaning and stripping processes include: pre-deposition native oxide removal (single wafer vapor, batch vapor, and single wafer dry), post-etch/ash residue removal (single wafer vapor), backside film removal (single-wafer wet spinner), highly selective oxide removal (single-wafer vapor) and post-deposition particle removal (single-wafer dry cryokinetic aerosol).

These important applications will continue to be required for 180 nm technologies on 300 mm wafers. In addition, new cleaning and stripping applications will develop in association with the use of copper metalization, low-k dielectrics and CMP in the back end of the line.

Single-wafer vapor

Single-wafer vapor and batch vapor processing have mainly focused on the use of anhydrous HF (AHF) with water vapor for native-oxide removal before thin-film deposition. A key advantage to AHF vapor processing for silicon surface preparation is the removal of native oxide without the formation of water spots typically seen with wet HF-last batch processing. The challenges of HF-last processing with 300 mm wafers may further stretch the capabilities of batch wet, resulting in an increased movement toward AHF vapor surface preparation. Another advantage to this technology is the use of gas phase chemicals, thus eliminating sources of surface contamination associated with DHF and significantly reducing the amount of chemicals used.

A key challenge of single-wafer vapor cleaning and stripping is low throughput relative to batch wet processes, though automation and multiple chamber clustering will help improve throughput for 300 mm, single-wafer equipment. It is possible that at 300 mm the benefits of low chemical consumption and low waste streams will start to outweigh the limitations of throughput.

Particle removal and yield enhancement

Brush scrubbers are finding relatively wide-spread application for post-CMP cleaning and post-deposition cleaning. The direct mechanical action of brush scrubbers is quite effective in detaching large particles from planar topographies of hard substrates or films. Particles that are in recesses however, are not removed, and scratching by hard particles could be particularly severe on soft films like organic or aerogel low-k dielectrics. Further, brushes have a short life, and a scrubber system is unlikely to reach the 1-hr/week preventative maintenance limit in the Unified 250 nm Specification. Significant improvements in brush-scrubber technology will be necessary to allow its widespread use in future 300 mm generations.

For single-wafer vapor and single-wafer dry chemical processes, particle removal poses a particularly difficult challenge. This challenge is being addressed by another single-wafer dry technology, cryokinetic-aerosol processing.¹³ Crystalline and cryokinetic aerosols are directed mainly at physical particle and residue removal, although there is evidence that CO₂ "snow" processes may chemically remove some organic contaminants. The two important steps in particle removal with cryokinetic aerosols are the same as in batch wet processing, detachment and transport. Both of these steps have been optimized for cryokinetic aerosol cleaning through process and equipment development. This technology has been shown to remove more than 95% of Si₃N₄ challenge particles at 0.15 µm, meeting the current particle removal requirements shown in Table 1.

Cryokinetic aerosol processing is now being used in 250 nm semiconductor manufacturing to achieve defect removal in areas where SC-1/megasonic cleaning has failed or is unacceptable. Increasing concerns with environmental safety and health as well as chemical compatibility materials issues (copper and low-k dielectrics) in the BEOL, which parallel the move to 300 mm wafers, will likely drive increased use of the cryokinetic aerosol technology.

Movement towards single-wafer clustering and environmentally friendly processes will have a significant impact on the development and implementation of new cleaning technologies for 300 mm wafer manufacturing.

Table 1. Batch Diffusion Pre-Clean Requirements for 300 mm Wafers
First product ship generation	250 nm	1998 250 nm	1998 250 nm	1997 180 nm	1999 130 nm	2003 100 nm	2006
Source		I300I1	Unified2 I300I | SELETE	1997 SIA3 1994 SIA	1997 SIA 1994 SIA	1997 SIA 1994 SIA	1997 SIA 1994 SIA
Attribute		Units
Yield target	%	60	60	60 90	60 90	60 90	60 90
Equipment parameters
IPA Drying		Yes	Yes
HF temperature control (ambient)°	C	<0.25	<±0.2
SC-x temperature control (50-80 °C)	° C	<0.5	<±0.5
HF chemical concentration control	Wt%	<2	<±2
SC-x chemical concentration control	Wt%	<10	<±10
Process targets
HF etch uniformity total variability	% (3 s)	4	<5	±4	±4	±4 to 6	±4 to 8
0.17 µm particle removal efficiency	%		90: Si powder	95: Si3 N4	95: Si3 N4	>95: Si 3N4	>95: Si 3N4
Water marks (HF last)	Count		none	@ 0.125 µm	@ 0.09 µm	@ 0.065 µm	@ 0.05 µm
Process characteristics
Metalic contamination:
Cr, Fe, Ni, Cu, Zn, Mn	Atoms/cm2	TBM*	<1x1010
Na, Mg, Al, K, Ca, etc.	Atoms/cm2	TBM	<1x1010
Ca, Cu, Cr, Fe, K, Mn, Na, Ni, etc	Atoms/cm2			5x109	4x109	3x109	1x109
Al, Ti, V, Zn	Atoms/cm2			5x1010	2.5x1010	2x1010	1x1010
Lifetime	µ sec		>200
Breakdown voltage	V		TBM
TDDB	sec		TBM
Surface roughness	nm RMS	TBM		0.15	0.1	0.1	<0.1
Organics	C atoms/cm2			1x1014	7x1013	5x1013	3.5x1013
Defect-PWP
In-film at 0.20 µm size	#/Wafer (/m2 )	3.5 (51)	<3.5 (51)
On bare silicon at 0.12µm size	#/Wafer (/m2 )	9.6 (142)	<9.6 (142)	<9.6 (142)**	<4.2 (71)**	<2.1 (36)**	<1 (15)**
Backside at 0.20 µm size	#/Wafer (/m2 )		<200 (3000)	@ 0.125 µm	@ 0.09 µm	@ 0.065 µm	@ 0.05 µm
Edge exclusion	mm	3		3	2	2	1
Cost/performance target
Throughput - wafer/hour	158	158
Tool capital cost - $M	2.5	2.5 | x 1.3**
MTBF - hour	1000	1000 |
MWBI - wafer		| 5000
MTTR - hour	3.3	3.3 |
Preventive maintenance	hr/wk	1.0	1.0 |
Consumables	$/Wafer pass	0.64	0.64 | x 1.25 ***
Area per tool	m2	8.4	8.4 | x1.35***
Support area per tool	m2	4.7	4.7 | x1.35***
CoO target
CoO objective	$/Wafer pass	1.5	1.5 | TBD
Production utilization	%	98.7
*To be measured **PWP estimate determined by multiplying the 250 nm Unified Specification by 0.5 per generation scaling factor used in the 1997 SIA Roadmap. ***Scaling factor times 200 mm determines the target value for 300 mm equipment.

References

1. International 300 mm Initiative, "Equipment Performance Metrics - Revision 3," Austin, Texas, 1997, p. 24.

2. International 300 mm Initiative, "Unified Equipment Performance Metrics for 0.25 mm Technology," Austin, Texas, 1997, p. 17.

3. Semiconductor Industry Association, San Jose, Calif., 1997, p. 17, 64, 68, 74, 116 and 164.

4. B. Fraser and M. Olesen, 1998 Semiconductor Pure Water and Chemicals Conference, M. Balazs Ed., Balazs Laboratory, Sunnyvale, Calif., 1998, p. 375.

5. S. Smith and K. Christenson, Cleaning Technology in Semiconductor Device Manufacturing, V. J. Ruzyllo and R. Novak, Eds., The Electrochemical Society, Pennington, N.J., PV 97-35, p. 544.

6. K. Christenson, 1996 Semiconductor Pure Water and Chemicals Conference, M. Balazs Ed., Balazs Laboratory, Sunnyvale, Calif., 1996, p. 289.

7. K. Christenson, Proc. 43rd Ann. Tech. Meet. of the IES, Institute of Environmental Sciences, Mount Prospect, Ill., 1997 p. 170.

8. T. Shimono et al., 8th Workshop on ULSI Ultra Clean Technology, Ultra Clean Society, 1990, p. 59.

9. T. Hattori, Cleaning Technology in Semiconductor Device Manufacturing, V. J. Ruzyllo and R. Novak, Eds., The Electrochemical Society, Pennington, N.J., PV 97-35, p. 3.

10. L. Loewenstein and P. Mertens, Cleaning Technology in Semiconductor Device Manufacturing, V. J. Ruzyllo and R. Novak, Eds., The Electrochemical Society, Pennington, N.J., PV 97-35, p. 89.

11. G. Gale and A. Busnaina, Particulate Science and Technology, 13, 1995, p. 197.

12. I300I Technology Transfer Document, #97093360A-ENG, 1997.

13. J.F. Weygand et al., Micro 15(4),1997, p. 47.

14. Semiconductor Industry Association, San Jose, Calif., 1994, p. 116.

	Kurt K. Christenson received his bachelor's degree in Physics from Bethel College and his master's and doctorate in Physics from the University of Illinois, Urbana. Christenson has been a senior staff engineer at FSI International since 1990. Phone: 612-448-8047 Fax: 612-448-1308 Email: kchristenson@fsi-intl.com
	Jeffery W. Butterbaugh is Applications Engineering Manager for Single Wafer Systems at FSI International. He received his bachelor's degree in Chemical Engineering from the University of Minnesota and his doctorate in Chemical Engineering from MIT. Phone: 612-448-8089 Fax: 612-361-7393 Email: jbutterbaugh@fsi-intl.com