Trends in Wafer Cleaning

		At a Glance
	Requirements of more stringent device specifications, environmental concerns and the move to new materials are prompting the development of dry cleaning techniques such as laser, aerosols and ozonated chemistries in parallel with the improvement of wet methods. The move to new materials is also forcing the advancement of new cleaning solutions. Standard chemistries for aluminum do not work for copper, and at 0.13 µm design rules, the transition to low k materials with dielectric constants in the 2.5 to 2.8 range bring additional challenges.

The days of using one cleaning process for virtually all steps are long gone. Today, in addition to removing particles, native oxides, organic contaminants, mobile ions and metallic impurities, the cleaning process can put back friendly materials for passivation. On a macroscopic level, cleaning covers resist stripping, post CMP and general purpose cleans for pre- and post-etch, depositions and diffusion. With each new device generation, the cleaning requirements become more stringent, and the number of cleans increase. For 64Mb 0.25 µm DRAM fabrication, 60 to 70 cleaning steps are required. At 0.18 µm design rules, 80 out of ~400 total steps will be cleaning. While the number of cleans increases, the requirement levels are also increasing for impurity concentrations, particle size and quantity, water and chemical usage and the amount of surface roughness for critical gate cleans.

Traditionally, cleaning has been concentrated in the front end of the line (FEOL) where active devices are exposed and more detailed cleans required. The back end of line (BEOL) has multiple metal layers requiring more specific cleans, such as removing particles and complex organic materials. This has typically been less of an issue than front-end cleans. However, the progression from 0.25 µm to 0.13 µm design rules has meant the addition of new metal layers. In general, every metal added will introduce three to five BEOL cleans depending on the process. With seven metal layers at 0.18 µm, the number of BEOL cleans is not only comparable to but is beginning to exceed the number of front-end cleans.

Particle removal

A primary challenge in FEOL cleans is the continuous reduction in the defect levels. As a rule, a "killer defect" is less than half the size of the device linewidth. For example, at 0.25 µm geometries, cleans must remove particles smaller than 0.12 µm and at 0.18 µm, 0.09 µm particles. The issue is that smaller particles are physically more difficult to remove, because it is harder to deliver the necessary force to minuscule dimensions. Thus more energy is required to remove smaller particles.

Megasonics is the most widely used approach to adding energy to the cleaning process. The physics behind how particles are removed however, is not well understood. A combination of an induced flow in the cleaning solution (called acoustic streaming), cavitation, the level of dissolved gases and oscillatory effects are all thought to contribute to particle removal performance.

A compliant cassette "grips" 300 mm wafers for transport to a wet clean process tank. (Source: SCP Global)

Despite the familiarity of megasonics, beyond a maximum level and ~6 sec of agitation, some say that damage to the wafer can occur. According to Steve Bay, chief technical officer at CFM (West Chester, Pa.), there is no evidence of this. He said that megasonic damage is more a function of implementation, not a theoretical limitation. If however, megasonics can damage wafers, this may prove to be a critical limitation for the removal of particles smaller than 0.1 µm.

To address this potential shortcoming associated with the megasonic process, a new technique has been developed by ProSys (Campbell, Calif.). By exciting ceramic piezoelectric crystals with a high-frequency AC voltage, the resulting vibrations generate an acoustic wave that provides the cleaning mechanism. As many as 16 piezoelectric crystals can be switched on and off in sequence, delivering pulsed megasonic energy up to 100 Hz.

Brush scrubbing

Brush scrubbing is considered one of the most effective methods for removing the slurry used in the CMP polishing process. It is used for particle reduction (Fig. 1) as well. Early versions of wafer scrubbers proved damaging to the wafer surface because of high pressure water sprays and nylon brushes. However, using brushes made of polyvinyl alcohol (PVA), a soft, highly compressible, sponge-like material, particle removal without damage to the surface of wafers can be achieved.

Both silicon and IC manufacturers have confirmed that PVA brush scrubbing is not only able to remove particles on the order of a micron but is effective for the removal of submicron particles as well. According to Dr. Diane Hymes, director of cleaning process technologies at OnTrak Systems (San Jose, Calif.), the brush scrubber's ability to clean with room temperature dilute solutions, non-toxic chemicals and/or DI water is well suited to the environmental and safety requirements of today and the even more stringent requirements of next generation manufacturing technologies.

Cryogenic cleaning

Fig. 1. No longer just for CMP cleaning, wafer scrubbing with a soft, sponge-like PVA brush can also clean submicron particles. (Source: OnTrak Systems)

With the mismatch of WIP and throughput and of technologies such as wet vs. dry and vacuum vs. ambient, the need for very specific spot cleans is coming into focus with new emphasis on dry processes such as vapor cleans and cryogenics. A 10-year-old technology, also referred to as aerosol cleaning, cryogenics uses either a CO₂ or an argon/nitrogen gas source.

Historically, the use of CO₂ aerosol cleaning for precision applications has been limited by problems with recontamination. Early systems used evaporative cooling, which would freeze the liquid droplet into a solid particle, thus distilling off the pure CO₂ and concentrating contaminants in the droplets. To address this issue, ATS Eco-Snow Systems (Livermore, Calif.) has designed a new nozzle that prevents the deposition of residual contaminants on the wafer surface. Their approach combines purified CO₂, specialized environmental control, ultraclean automation and process control with advanced nozzle technology. The Eco-Snow technique has successfully removed particles down to 0.15 µm with concentration levels <0.05 particles/cm², noted Tom Kosic, general manager.

An argon/nitrogen aerosol mix was orginally developed at IBM because of the inherently higher purity of gaseous sources. FSI's (Chaska, Minn.) ARIES (Fig. 2) pre-cools the gases with liquid nitrogen at high pressures and forms the solid aerosols in a vacuum chamber. Wafers are then scanned under a linear nozzle where high velocity aerosols, >100 m/sec, clean the surface. Greater than 99% removal of surface particles larger than 0.15 µm have been demonstrated, noted Dan Syverson, single wafer systems marketing manager at FSI. Applied to areas where conventional cleaning methods are limited such as gate stacks and interconnects, yield improvements from two to 8% have been indicated, translating to millions of dollars in revenues per month.

Laser cleans

Fig. 2. Wafers are cleaned as they pass under a stream of frozen argon/nitrogen crystals in an ARIES process chamber. (Source: FSI International)

Laser cleaning can reduce particulates from a wafer surface without the use of water or chemicals and with no wetability limitations or hazardous wastes. One approach used at Radiance Services Co. (Bethesda, Md.) implements a KrF excimer laser to lift the contaminant from the surface and a flowing inert gas to sweep it away. Surface micro-roughening by the process is less than 1Å, comparable to the native roughness of a silicon wafer, noted Paul Castrucci, senior adviser to Radiance. Removal of particles and flakes from 80 µm to 0.09 µm has been demonstrated as well as removal of CMP slurry residue, photo resist films, chemical hazes and metallic ions. It has been hypothesized that cleaning occurs from, among various mechanisms, a combination of light-induced surface phonons breaking particle bonds through energy absorption, charge transfers between the surface and the particle and photo decomposition of the particle.

Based on the results, Castrucci speculated that the greatest benefit of the Radiance process may be in test yield improvements. Because it is capable of cleaning defects less than half the size of conventional wet cleaning, the process may become a yield enabler for 0.18 µm design rules and below. Studies continue at Radiance and Rutherford Appleton Laboratories (Chilton,UK) to further evaluate laser gas cleaning.

The Interuniversity Microelectronics Center (IMEC, Leuven, Belgium) evaluated dry laser cleaning that demonstrated ~84% removal of 1.0 micron SiO₂ and only ~12% removal of 0.3 µm SiO₂ particles.¹ This is in qualitative agreement with theoretical calculations showing the existence of a size threshold for particle removal by dry laser cleaning, a scientist at IMEC noted. The removal of 0.3 µm SiO₂ particles reached ~88% when wafers were exposed to air saturated with moisture prior to laser processing. The researchers attributed this to the explosive evaporation of capillary condensed water.

Environmental solutions

There is an industry-wide drive to address environmental issues by reducing chemical usage. One approach used by a number of companies including CFM, FSI International, SCP (Boise, Idaho), Tokyo Electron America (TEA, Austin, Texas) and VERTEQ (Santa Ana, Calif.) is changing the ratios of existing chemistries. For example, the RCA-type clean that has been the basic set of chemicals used in the industry for the past 20 years typically consists of an SC-1 mixture of 1:1:5 ammonia, peroxide, water mixture. Today, dilute chemistries can increase the amount of water by a factor of 10 to 1:50. With the addition of "optimized megasonics," the same level of clean or better can be achieved in a shorter time, noted Mark Hall, FEOL process manager at SCP.

A reduction in surface roughness also can be seen when using dilute chemistries. Atomic force microscopy (AFM) studies indicate that a standard SC-1, 1:1:5 ratio clean at temperatures >658C has an rms roughness of >1.5 Å (Fig. 3). With 50:1 dilute chemistries and temperatures <508C, rms roughness was reduced by a factor of three to <0.5 Å.

Further dissolutions have also been successful. At CFM, effective cleaning has been achieved with 80 parts DI water to one part cleaning chemistries. VERTEQ's ultra-dilute technology uses several 100:1 dissolutions and typically half the water of traditional cleaning. National Semiconductor (Santa Clara, Calif.) has demonstrated the effectiveness of these ratios in cleaning thin gate oxides. ³

Another strategy to chemical reduction is changing the cleaning sequence. For example, a pre-diffusion or oxide cleaning that may contain both metallic contaminants and particles can be modified from a four-step process to a three. A cleaning sequence may consist of:

Fig. 3. Surface roughness comparing (a) standard 1:1:5 cleans to (b) 1:2:50 ratios indicate a factor of three improvement using dilute chemistries. (Source: SCP Global)

• sulphuric acid for organics,
• HF for oxides,
• SC-1 for particles and
• SC-2 for metals.

By adding HCl for metal removal to the HF step, the sequence could be shortened with the elimination of the final SC-2 metal removal.

The processing of the cleaning chemistries themselves to achieve 5-6 nines purity may be a another less obvious area to address environmental concerns. According to John D. Kelly, diffusion/wet engineer, formerly of Twinstar (Richardson, Texas), the purity of cleaning solvents currently used may be good for the next 10 years. Though a point-of-use filter may be required for some future generation of devices, the cost and chemical processing for higher purities is not necessary.

Ozonated chemistries

Ozonated chemistries can provide an environmentally friendly alternative to the use of sulfuric acid and harmful solvent strippers. Several research groups have investigated the possible use of this technology for the removal of organic films. In particular, IMEC has developed a moist ozone gas-phase process² that is designed to enhance the removal efficiency of photoresist and organic post-etch residues. An O₃ diffuser is immersed in heated DI water that can be spiked with additives like acetic acid. The wafers are then positioned directly above the liquid and exposed to a moist O₃ ambient. This forms a thin condensation layer on the wafer that reduces the diffusion limitation and allows the short-lived, reactive O₃ components to reach the wafer surface.

Comparisons of a 45 min O₃ dry strip to a 10 min moist O₃ gas-phase process indicate the effectiveness of this technique (Fig.4), noted Gilbert Declerck, vice president, Advanced Semiconductor Processing Division at IMEC. Test results suggest that this process also may be used to eliminate all sulfuric acid-based process steps in IC production, Declerck said.

Hybrid systems

Fig. 4. SEMs compare 0.4 µm via structures following (top) a 10 min O3 moist gas phase cleaning with acetic acid added with (bottom) a 45 min O2 dry strip process. (Source: IMEC)

Post-via etch residue is one of the most demanding cleaning applications. There are questions as to whether current dry plasma technologies alone can meet the cleaning requirements of the high aspect ratios seen in advanced manufacturing. At 0.18 µm ratios as high as 6:1 are expected. Especially difficult are vias in which the AR-coated layer is etched away, exposing the underlying aluminum or copper metal lines. Dry plasma has been successful for post-metal, post-poly and post-contact etch residue removal.

For post-via however, the combination of rf and microwave has shown promise in enhancing the dry cleaning process. The rf source provides the anisotropic element to clean the bottom, and the microwave source provides the isotropic element to clean the sidewalls. This hybrid dry source is useful for post-poly and post-contact cleaning by enhancing the clean with a "soft" rf component while primarily using downstream microwave to minimize plasma charge damage, according to Andy Kirkpatrick, director of marketing at GaSonics International (San Jose, Calif.).

Another hybrid system consisting of microwave plasma technologies and non-aqueous "moist" chemistries has also been developed by GaSonics to clean high aspect ratio vias. Following a microwave downstream plasma to pre-treat the residue is a densified fluid cleaning (DFC) that uses a gaseous source, yet performs the cleaning in the liquid phase, Kirkpatrick said. This combination gives DFC the capability to enter small areas as a gaseous chemical and then liquefy for residue removal. Cleaning of 6:1 aspect ratios has been demonstrated, Kirkpatrick noted.

New materials

The technology development surrounding the replacement of SiO₂ -based dielectrics with low k materials (below 3.0) and aluminum with copper is pervasive in the industry. These new materials present the biggest challenge for cleaning as well. Though no decision has been made, the primary dielectric for interconnects is likely to be an organic film. For the cleaning community, this raises a flag, because many of the cleaning processes are designed to remove organic materials as contaminants. Therefore, one cannot be removed without attacking the other.

With oxide dielectrics, it is possible to configure certain selectivities into the chemistry, to remove organic resist films, for example, but leave the SiO₂ untouched. However, it is not clear if the same kind of selectivities exist with organic dielectrics, Syverson noted. In addition to precluding the use of ashing techniques to remove resists, the compatibility of RCA-type chemistries is in question. Companies that have concentrated on fine-tuning cleaning processes are now forced to create new technologies.

Copper

The biggest cleaning issue with copper is preventing it from getting into the front-end processing where it can destroy the integrity of the gate oxide, creating leakage currents. Surface defects such as roughening, also can be induced with copper contaminants. Back- to- front-end contamination can occur when copper flakes off the back of a wafer in solution during wet processing and through tools such as defect review and metrology stations. Studies are underway to determine where to focus cleaning efforts. For example, the control of flaking through a combination of improved copper deposition techniques and post-metal cleaning techniques is being examined. One straight-forward approach currently under investigation is a wipe-down procedure of metrology tools following exposure to copper wafers.

Another technique being evaluated to prevent cross-contamination is adding HCl to HF to help ensure the cleaning of copper contaminants, Hall noted. The addition of HCl prevents copper, due to its electronegative properties, from plating onto the silicon by effectively tying up the Cu metal impurities in solution before they have the chance to plate.

Further studies are designed to bring about greater understanding of the fundamentals of cross contamination. For example, it was previously thought that any wet cleaning tool exposed to copper would contaminate all wafers that subsequently went through that bench. That myth has essentially been dispelled, said John Rosato, BEDL process manager at SCP. Furthermore, processing a front-end wafer on the same equipment that a back-end wafer has been run through does not necessarily add to cross contamination, Rosato said. Clearly, most copper cross contamination will occur during CMP.

Wrap-up

According to FSI's Syverson, the ultimate solutions to high, >6:1, aspect ratio features are non-wet, all-dry cleaning processes. While wet chemical cleans are being extended, the question remains, is debris being adequately rinsed and removed from the bottom of narrow, deep trenches? Research is underway to develop all-dry cleans using various energy sources such as UV and IR coupled with a variety of gases. With the inherent selectivity requirements involved in these approaches, an increasingly more complex approach to cleaning will likely result.

Wafer cleaning technology is undergoing several major transitions driven by new materials, environmental/cost issues and continued tightening of specifications. So in addition to more complex solutions, according to Don Burkman, cleaning systems business unit manager at TEA, the end result is likely to be a more diverse set of technology solutions that are tailored to these specific application needs.

References

1. G. Vereecke, et. al., 1998 Proceedings, Institute of Environmental Sciences and Technology.

2. S. DeGendt, et. al., IEEE Symposium on VLSI Technology, Honolulu, Hawaii, June 1998.

3. T. Dhayagude,et. al., MRS, vol. 477, Spring 1997.