Keeping Contaminants at Bay during Thermal Processing
New approach to controlling contamination during long furnace processes reduces downtime needed to clean furnace tubes
Laura Peters, Senior Editor -- Semiconductor International, 8/1/1998
A new technique addresses the need to keep alkali elements from the wafer surface during processing in diffusion furnaces. Available for retrofit to existing furnaces, the Promecon technology (see figure) from an Israeli firm, Sizary, is a software and hardware package using an electric field to prevent the migration of ionic contaminants such as sodium (Na), potassium (K) and lithium (Li) to the wafer surface. In addition, because such contamination can come from the furnace's quartz tube, use of this technique should also reduce downtime needed to clean the furnace tube with chlorine gas or chlorine-based steam.
The first furnace available with the technology is Sizary's Promecon MBFR-100 minibatch fast-ramp furnace. Data from hundreds of wafer runs with Promecon was evaluated under the same conditions with no field applied (Table). Contamination levels were determined using secondary ion mass spectroscopy (SIMS) analysis and verified using traditional C-V testing.
SIMS levels using the Promecon method were all below 500 counts/sec, and depending on the process conditions, were as much as a magnitude lower than in furnaces where no field was applied. For instance, the peak reading for K at atmospheric pressure and 9008C for one hour was 3000 counts/sec, whereas it was 300 counts/sec when the Promecon technique was employed. At reduced pressure (0.7 Torr), 9008C for one hour, again there was an order of magnitude difference in contamination levels. It was only at high vacuum (10-5 Torr) that contamination levels became comparable.
One shortcoming to this approach is the high detection limit of the C-V method (approximately 1011 atoms/ cm2), which corresponds to a SIMS reading of 500 counts/sec. A second challenge arises from the fact that the C-V method reports total levels of ionic contamination, unable to differentiate between species.
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| Based on the application of an electric field during thermal processing, the technique prevents migration of alkali metals including sodium, potassium and lithium. |
As shown in the table, high C-V readings correspond to high counts of one or more alkali ion species in the SIMS plot. Also, in "no field" and "Promecon" conditions, the levels in the SIMS plots are below 500 counts/sec, corresponding to levels of below 531010 atoms/cm 2 in the C-V plot. These levels are within the measurement error in the C-V system. The effect of the reverse field is however, dramatic, and there is a good correlation between the C-V and SIMS readings. This set of results also confirms the reliability of SIMS measurements used throughout this work.
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Table: Contamination Results |
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| Process conditions | Electric field direction |
Total ions from C-V (atoms/cm231010) |
SIMS Li peak reading (counts/sec) | SIMS Na peak reading (counts/sec) |
SIMS |
| 900° C 1 hr | Reversed | 24-45 | 90 | 100 | 25,000 |
| ATM pressure | No field | 4-8 | 200 | 120 | 3000 |
| N2 2000 sccm | Promecon | 2-8 | 250 | 130 | 300 |
| 900° C 1 hr | Reversed | 250-350 | 8000 | 1000 | 20,000 |
| 0.7 Torr | No field | 2-4 | 10 | 300 | 400 |
| Ar, 140 sccm | Promecon | 1-4 | 8 | 20 | 30 |
| 900° C 1 hr | Reversed | Over 750 | 300,000 | 1000 | 10,000 |
| 105 Torr | No field | 4-6 | 120 | 10 | 9 |
| (Hi-vacuum) no gas flow | Promecon | 5-6 | 80 | 9 | 20 |
Company News
W.L. Gore (Eau Claire, Wis.) granted a patent and technology license to NTK Technical Ceramics (Nagoya, Japan) to manufacture IC packages using Gore's organic technology and MICROLAM dielectrics.A new company, Inspectech Ltd. (Carmiel, Israel), has been formed to produce equipment for inspecting diced 300 mm wafers.
F&K Delvotec (Ottobrunn, Germany) is shipping an order for Model 6400 wire bonders to Hewlett Packard (Colorado Springs, Colo.). The company received orders for Model 6400 and Model 4400 die bonders from RF Monolithics (Dallas, Texas).
PADS Software (Marlborough, Mass.), along with InterChip Systems (North Andover, Mass.), re-leased a new package layout software line, PowerBGA. The first offering focuses on direct chip attachment to PC boards and will expand to BGAs, CSPs and laminate MCMs.
Integrated Packaging Assembly Corp. (IPAC, San Jose, Calif.) has obtained a $7.5 million commitment for equipment financing. Immediately available was $3 million, with the remainder to become available after IPAC raises an additional $10 million in equity or other financing.
ESEC (Asia Pacific) Pte. Ltd. (Singapore, Malaysia) signed a $30 million contract to supply wire and die bonders to PT Astra Microtronics Technology (AMT, Batam, Indonesia). The agreement covers equipment deliveries from July 1998 through June 2000.
Walsin Advanced Electronics (Kaosiung, Taiwan), Winbond Electronics (Hsinchu, Taiwan), Toshiba Corp. and Mitsui & Co. (Tokyo, Japan) are funding a new company, Walton Advanced Electronics Ltd. (WAE, Kaohsiung, Taiwan), to assemble 64 Mb DRAM and other memory devices.
Glass Serves as Wafer Level Packaging
ShellCase Ltd. (Jerusalem, Israel) has developed a wafer level chip scale packaging technology, ShellPack, in which a thinned die is sandwiched between two glass plates. The "shell" is 300 to 500 mm thick and no more than 100 mm longer or wider than the die. It is intended for ultrathin applications like smart cards and portable products. It is also being offered as a replacement for direct chip attach (DCA). The packaged device is said to have 15% greater break resistance than bare silicon of the same thickness.
The wafer is bonded to a glass plate, and it is lapped down to a 100 mm thickness. Etching is then performed to thin the wafer to 50 mm and to separate the dice (Figure). Another glass plate is bonded to the backside of the devices, encapsulating the devices in epoxy. The assembly is then flipped, and grooves are made in the front side glass, exposing the I/O pads on the devices. Metal is evaporated on the front side and patterned to make the I/O connections.
Since the package completely encases the die in adhesive, the die is protected on all sides before the devices are singulated. The packaged device is about the same size and thickness as a bare die, but it does not require as much care in handling. With the glass and a choice of a transparent epoxy, optoelectronic devices can be packaged without special windows.
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| ShellCases's technology starts by bonding a wafer face down onto a plate of glass (a). After thinning and singulation by etching, a second plate is bonded to the back, encapsulating the devices in adhesive (b). Grooves are made in the first plate, exposing the bond pads on the dice, and metal is deposited and patterned for the I/Os (c) before singulation. |
One practical concern for smart cards is reverse engineering. Many believe that the software technology used on smart card chips is sufficient to defeat "black box" reverse engineering of a stolen card. However, if the card is taken apart and the chip removed, the chip can be reverse engineered with available equipment. The ShellPack package is designed to be resistant to being opened. The company claims that it cannot be taken apart without destroying the chip.
Testing and burn-in of the devices is done at the wafer level, so the packaged parts are ready to use. The leads are also very short, reducing parasitics and improving electrical performance. Thermal paths to air or to a heat sink are also very short, aiding in heat removal. The package can be attached to a PC board using conventional soldering rather than TAB or wirebonding, so the part requires no additional contact area.
Lead counts for a 12.5312.5 mm die in this package can be as high as 320. Peripheral and BGA configurations may be used with lead pitches from 0.3 to 0.5 mm. For high heat dissipation applications, aluminum nitride can be used instead of glass.
