Yield Models Link Inspection Data with Probe Yields
The long-awaited tie between in-line inspection data and probe yields is here.
Laura Peters, Senior Editor -- Semiconductor International, 4/1/1998
Two new in-line yield prediction methodologies, which take into account device design sensitivity to defects, accurately predict fab yields using patterned wafer inspection data. This is the work of engineers from KLA-Tencor (San Jose, Calif.), AMD (Austin, Texas), Carnegie Mellon University (Pittsburgh, Pa.) and Stanford University (Palo Alto, Calif). These yield models were able to match actual fab yields with a 3% accuracy. The first model used a multilayer critical area method, while the second used a kill ratio method separating defects by type and size. Such yield prediction models could allow fab planners to accurately predict yields before first silicon -- given the fab's current defect densities.
By making comparisons with actual fab data at three critical levels (the polysilicon gate, Metal 1 and Metal 2 interconnects), the group demonstrated how its critical area model can be used across a variety of device types, including ASIC, telecommunications devices, microprocessors and audio processors. Results were summarized in a paper published in the February 1998 issue of IEEE's Transactions on Semiconductor Manufacturing.
The critical area based model quantifies layout sensitivity to random spot defects that cause shorts. Critical area is the area of a die on which, if the center of a defect of a given size lands (assuming a circular defect), then the defect will cause a short. There is a unique critical area for each defect size and each layer of the device. A Poisson-based yield model is used, together with a design rule checking tool and a software tool for critical area extraction, to predict overall functional yield. A flow chart of the methodology is shown in Figure 1. Using a scaling factor, the critical area extraction method compensates for variations in critical dimensions between the device layout and the manufactured dimensions.
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| 1. The model compares predicted yield (using the design layout and inspection data) with probe failures. |
The data were then classified by x and y dimensions, true defect area and defect type (using defect size histograms or by fitting distributions to raw defect size data). By combining defect density and size distribution per defect type with the critical area function, yield impact per layer per defect type is calculated. Using only the telecommunications device, the predicted yields are compared with actual probe test yields by retrieving test bin information from the tester database using only the die with the random defect failures (e.g., intralayer shorts).
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| 2. Using the critical area model, predicted yields came within 3% of the actual yields for most work weeks. |
The second model, the empirically derived kill ratio approach, matched the in-line wafer inspection and classification data with the corresponding bin/sort yield data. The group used moving averages both on the defect size and yield data to obtain the average defect size and its average kill ratio. Results using this model agreed well with the critical area model.
