Chip traceability implementation

"Chip traceability makes it possible to maintain a complete device history from bare silicon to packaged chip."

Joe Savarese, Electroglas Inc., Santa Clara, Calif. -- Semiconductor International, 4/1/1998

For far too long, the semiconductor industry has addressed IC fabrication not as a single-factory production challenge, but as a process occurring in two separate factories -- wafer fabrication (front-end) and chip assembly and test (back-end). In the multitude of process and product verification steps required by the entire production cycle, this front-end/back-end dichotomy has created a gap where critical yield management fab process data are lost. With the complexity of IC production increasing to address smaller geometries and larger substrates, the time has come to bridge that gap.

Efforts toward linking front-end to back-end have been under way for the past two years with the SEMI Traceability Committee. This group has taken pioneering steps to make it possible for the semiconductor manufacturing community to trace the identity of individual die through an entire production cycle by implementing chip traceability in back-end manufacturing.

Wafer traceability in front-end processing already exists and is comprehensive, with physical tracking via wafer bar codes and wafer die maps. Data from every step -- metrology to the sort floor -- are collected, analyzed and correlated by sophisticated yield management software to form an effective process history. Information extracted from these automatically generated reports is used to optimize yield. Currently, the wealth of information and yield management potential are lost to the back-end engineer when the wafer is cut into individual die.

The concept behind chip traceability is to build a data and information bridge linking the fab's test databases with the databases generated during assembly and final test, making it possible to maintain a truly complete device history from bare silicon to packaged chip. By extending the data record on an individual die, the test databases at wafer sort and at final test can be compared to identify and investigate any degradation that took place during the assembly process.

Maintaining a record of an individual die's test results at the sort floor allows correlations to later testing, which highlight and help track down problems in chip assembly. For example, a micro-crack introduced during chip assembly may propagate and degrade the performance of a chip between sort floor test and final test. By finding this kind of problem early, it is possible to prevent the chip from further failing under extended use. Maintaining a record of each die is especially important with devices that have been value binned.

The complete information set would also be accessible to engineers conducting failure analysis (FA) in the future, investigating chip security and implementing defect containment strategies. Because the data can be tracked from assembly operations to the fab and back to the original ingot (or even to the IC's CAD design database to help understand a processing problem), a coordinated, efficient and accountable manufacturing process is formed.

Chip traceability implementation

Setting standards to make chip traceability possible and practical has been a focus of the SEMI Traceability Committee. The product of this committee is a standard for premarking leadframes with a two-dimensional data matrix. Current intelligent assembly equipment can use data matrix readers to read the coded information to establish a WIP and yield management database for test and assembly processes.

Die attach

Die attach machines must be wafer map driven and capable of reading the data matrix code on the premarked leadframe. When the bond head selects a die from given coordinates, the machine reads the code and updates the wafer map with the number corresponding to the leadframe location. This process adds a field to the database, corresponding to the code of each package. The die can then be tracked to the database, at any time, by reading the data matrix code from the final package.

Trim and form

At trim and form, the code must be transferred from the leadframe to the outside of the chip package, since the place where the code was originally placed is cut off at this stage. Achieving this transfer requires a data matrix reader, as well as a method of permanently embedding the code on the outside of the package, such as a laser marker. Now, with the same data matrix code on the outside of the packaged chips, the chips can be traced -- no matter where they go -- back to their entire journey through the fab.

Benefits of chip traceability

By keeping track of which chip is processed where, equipment maintenance and other corrective actions can take place at an early stage in both the wafer fab and the assembly and final test areas of IC manufacturing. Test data anomalies can be recognized instantly, allowing more effective decision making and corrective actions before more chips are affected. Since the fab and assembly data are now bridged, corrective action can be identified and take place anywhere in the manufacturing chain.

Chip traceability is a technology for today and the future that will empower new processes in chip manufacturing. Some benefits have been discussed here, and, as applications for such a process enhancement emerge, many more benefits will be discovered. The value derived from chip traceability will far exceed any cost impact on assembly equipment because it is much more than just an economically sound idea. Chip traceability is a good manufacturing technique today and will be a necessary technique tomorrow.