Triple Well Applications Profit From MeV Implant Technology

		At a Glance
	Three strategies presently exist for fabricating triple well structures: diffused, hybrid and MeV. The decision to migrate a process flow to the most advanced of these three options should be based on the benefits associated with the key fab drivers of yield, cost, cycle time and throughput. MeV triple wells offer attractive benefits in all these areas.

The application of triple well structures provides important advantages to several different CMOS devices. They include memory (DRAM, flash and SRAM) and embedded CMOS technologies with memory and logic on the same chip.

Because of market forces, more and more companies are looking to non-DRAM products for the future.¹ Of the established flash manufacturers, most have embraced some type of triple well technology, and 75% of the 64Mb DRAM generation devices use triple well structures.² SRAM on p-type substrates is also moving to triple well as reported,³ as are embedded memory and logic devices.⁴

To take full advantage of the leverage that triple wells provide, high-energy (MeV) ion implantation is preferred over other approaches. Classic diffused well technologies demand prohibitively long thermal cycles at high temperatures (>1150Å). Retrograde wells engineered through MeV scale implants require a fraction of the thermal budget (<950Å), provide greater packing densities, are less expensive to manufacture, outperform diffused well structures and promote productivity improvements via chained implants.

History of triple well structures

The early work in triple wells was presented in 1989 by Fujii, et al., of Toshiba.⁵ The enabling characteristic of the 16Mb DRAM fabricated with this process was the added degree of freedom associated with independent optimization of n-well and p-well biases. This early work was carried out on an n substrate with no epi layers. The 'third' well in the processing scenario was a relatively shallow n-well implanted into a much deeper p-well. The transistors fabricated in these wells were the PMOS of the CMOS pairs used in the peripheral circuits.

Continued development of this process was later applied to SRAMs where p substrates were used. SRAMs are particularly sensitive to soft error rate. Triple wells provided SRAMs with a 10x to 100x improvement in SER.

 Currently, triple well technology has applications within every type of CMOS circuit with the exception of pure logic. For flash memory, triple wells eliminate the need for an additional power supply and reduce chip size by 30%.⁴ In DRAM and SRAM circuits, the bulk of the transistors are in the memory array. However, the peripheral control circuitry requires multiple transistor types, which triple wells enable. Embedded CMOS circuits will have varying ratios of logic and memory on the same chip and require multiple transistor types as well. Straight logic is based solely on the simple CMOS pair, and therefore there is no overriding need to go to triple well technology here. There are additional performance advantages that triple wells provide, which will be reviewed in greater detail later in this paper.

Triple well processing

There are three methods of forming triple wells: diffused triple well, hybrid triple well and MeV (retrograde) triple well. The process technology employed by any one device manufacturer is based on that company's cost drivers, performance drivers and ultimately, their migration strategy.

High-energy implantation for triple wells is enabled through modern acceleration technology. Pictured here is a portion of the Genus DC Tandetron accelerator.

Diffused triple wells have been reported for memory applications by Toshiba (DRAM, SRAM, flash and merged memory/logic) and AMD (flash).⁴ They are formed by standard low-energy ion implantation at energies of <250 keV, followed by high temperature (1100-1200Å) diffusion furnace drive-in for 4-24 hrs. The longer drive-in times are required in order to form a 6 µm deep n-well. The high-temperature anneal also serves as a denudation step. This deep junction depth is required to prevent depletion region punch through from the isolated p-well to the substrate. This breakdown voltage can be >20 V, depending on the application and the maximum voltages present in the circuit.

Hybrid triple wells have been reported by LG and are formed by the combination of both sub-MeV high-energy ion implantation and moderate thermal diffusion/anneals at 1000- 1100Å for 1-4 hrs.⁶ This can be done in conjunction with the LOCOS isolation process to achieve both well drive-in and denudation steps.

True MeV retrograde triple wells have been reported by IBM⁷, Mitsubishi⁸ and LG⁶ for DRAMs, ST⁹ for flash and Micron³ for SRAM and are formed by MeV ion implantation in the 2-3 MeV energy range. Typically, this process forms a 2.5-3.5 µm deep buried n-well with a retrograde (subsurface peak concentration) dopant profile. In order to pattern and block this deep implant, thick photoresist is required in the 3.5-5.5 µm range. Thermal diffusion treatment is not required, and dopant activation and implant damage recovery can be achieved by the subsequent thermal processing, such as the gate oxidation step. However, since there is no high-temperature thermal cycle, one must engineer a high-temperature denuding step into the process or use pre-denuded wafers to ensure that there are no near surface bulk defects such as oxygen precipitates. If LOCOS isolation is utilized, then the LOCOS oxidation process can be modified to accomplish the required denudation. If shallow-trench isolation is used, then a separate denudation step will be required.

MeV retrograde triple well technology holds several advantages over the alternatives. There is a negligible thermal budget, which is important for 200 mm and especially 300 mm wafer processing. Process simplification and reduced manufacturing costs can be realized. Finally, improved device performance results from retrograde dopant profile of the well structures. However, substrate defect engineering must be optimized to ensure wafer denuded zone formation and gettering. High-temperature denudation or low oxygen content wafers are recommended for near surface defect control to ensure a high-quality gate oxide and low junction leakage.¹⁰

Impetus for change to MeV

Any change in device fab processing, represented by either a new process flow or tool set, has to be justified on a combined basis of the four fundamental fab drivers:

Yield -- raw performance per die or total good die per wafer. Improved yield has a direct impact on cost-of-ownership and productivity.

Cost -- the cost to manufacture a device directly affects the margins and a company's profitability.

Cycle time -- the total amount of time required for processing a particular process or process segment. Reduced cycle time equates to improved productivity and more cycles of learning per unit time.

Throughput -- the measure of the raw number of wafers that pass through a particular point in the process. High throughput minimizes the potential for constraints and increases productivity.

1. A retrograde (subsurface peak concentration) deep n-well is formed using an MeV ion implant. Since no diffusion is required to form the well, the process has a negligible thermal budget.

Retrograde triple well processing allows the formation of a buried n-well beneath selected n- and p-wells without surface compensation of dopants, which can lead to improved device performance in the areas of latch-up, soft error rate and alpha particle immunity (Fig. 1). Additionally, improved device packing density results since no lateral dopant diffusion occurs.

Triple well structures electrically isolate the wells from the substrate and allow the optimization of bias potentials for both n- and p-wells. When used to fabricate flash memory, power consumption is reduced (dual power supply voltages are eliminated allowing single low voltage power supply) and packing density is increased by eliminating the PMOS transfer gate in the row decoder circuit.⁴ DRAMs benefit through n-well and p-well bias optimization, back gate bias avoidance and minimization of junction capacitance.⁸ Through triple wells, logic devices can utilize embedded flash, SRAM and DRAM and will become robust against alpha particle induced soft errors.

Minimization of thermal budget is a key element of MeV triple wells and has a direct impact on yield issues. Low to zero thermal budget processing is critical to minimize bulk wafer or epi-wafer thermal-induced stresses. Thermal processing can lead to wafer warpage, slip and ultimately, wafer breakage. Wafer bow and warp have been shown to generate downstream problems with photolithography CMP and backgrind.¹¹ Wafer shape will affect flatness in certain situations negating tight raw wafer thickness specifications necessary for 0.25 µm (250 nm) processing and beyond. This is a problem that will become exacerbated with the move to 300 mm substrates. Not only will 300 mm wafers be more sensitive mechanically to thermal-induced stresses, but the almost certain parallel move toward finer linewidths to the 0.18 µm (180 nm) node will make wafer shape control paramount.

Cost and cycle time

2. A triple well MeV implant strategy enables the elimination of up to three masking steps, which equates to 24 processing steps and up to $125 in savings per 200 mm wafer.

Up to three masking steps can be eliminated, which equates to 24 processing steps and up to $125 in savings per 200 mm wafer that can be realized (Fig. 2). Elimination of 52 process hours, five furnace anneal steps, three masking levels and the associated clean and metrology steps add up to significant capital equipment cost savings and space, reducing overall manufacturing costs by up to 12%.

With continued pressure to reduce manufacturing costs and process complexity, one approach is through the migration to Buried Implanter Layer for Lateral Isolation (BILLI) triple well per Figure 1 and as reported by LG.⁶ In comparing hybrid, MeV and BILLI triple well, LG reported no degradation in breakdown voltage. In fact, an improvement in short channel effects was observed. The BILLI triple well eliminates the p-well mask therefore one mask level; however, for some triple well applications it could reduce two mask levels by either changing substrate type or using phosphorus rather than boron for creation of the BILLI layer.¹² A cross section of the modeled BILLI triple well structure is illustrated in Figure 3.

3. The BILLI triple well structure provides more isolation without adding another masking step.

Throughput

The implementation of MeV technology can provide tremendous leverage in the raw throughput interpreted as the number of implants per hour. Through the use of chained implants, several implant steps can be performed in series without unloading the wafers from the process chamber.

The use of photoresist as an implant mask has been in use for years. However, the application of photoresist for high-energy implant use has several unique issues associated with it.

In order to mask higher energy implants, it is necessary to use much thicker resist for effectiveness. For MeV implants, which may reach as high as 3 MeV for some triple well applications, the projected range into bare silicon will be 2-4 µm. In order to effectively mask this implant, a resist thickness of 3.5-5.5 µm will be required.

When modeling resist thickness for implant, typically the composition of the material is taken into account to predetermine the density. However, it is not unusual for the practical density to be greater than the modeled density because of pre-implant softbake. Therefore, it is required that resist density be determined empirically. The difference in density between modeled and empirical values for a standard resist might be as much as 30%. Once the actual density value has been determined, a range table can be derived for the resist which will aid in determining the proper resist thickness.

The thickness of the resist in concert with the nature of high-energy beams creates a problem with outgassed material that is not a concern for lower energy implants. There is a directly proportional relationship to both beam current and ion energy to outgassed material. Since the phenomena is due to atomic bond breaking of the resist by the ion beam, the wafer temperature is an issue only to minimize carbonization and to facilitate ashing.

4. Outgassed photoresist from high-energy implanting increases chamber pressure and causes dose errors.

Outgassed material from photoresist into an ion implanter's process chamber will increase the partial pressures of hydrogen, nitrogen, water, hydrocarbons and other materials quite dramatically. If, for example, the total pressure increase approaches 3x10^-5 Torr (Fig. 4) for 1 MeV implants, then dose errors will surface. Random charge exchange resulting from the partial pressure increases will cause unwanted ionization and neutralization of the ion beam before it reaches the dosimetry Faraday. This will inadvertently confuse the dosimetry system creating the dose errors. To minimize this, it is generally accepted that the implant tool must be designed to keep the pressure below the critical level. The best way to do this is via a large volume process chamber and direct cryopumping.

Energy and dose requirements

5. The best p-well isolation, as measured by p-well to p-substrate breakdown, BVcbo, occurs when the deep n-well implant is done with a minimum dose at a maximum energy.

Typical modern triple well processes are all implanted. The deep n-well that forms the added isolation of the third well can require as much as 3 MeV of energy at a dose of 1x10¹³ to 5x10¹³. Additionally, the Boron p-well, which is implanted into the deep n-well, will require up to 1 MeV at a dose of 1x10¹³ to 5x10¹³. The key parameter for control is the breakdown voltage from the isolated p-well to the p substrate. The deep n-well energy and dose can be manipulated to achieve the desired requirement. The highest breakdown voltage is achieved with the highest energy and the lowest dose (Fig. 5).

Summary

Triple well structures have been in use for several years now. Their benefits are extensive and well documented. There currently exist three strategies for fabrication of triple well structures: diffused, hybrid and MeV. The decision to migrate a process flow to the most advanced of these three options should be based on the benefits associated to the key fab drivers of yield, cost, cycle time and throughput. As illustrated, MeV triple wells offer attractive benefits to all these key drivers.

When implementing MeV triple wells, the key considerations are photoresist outgassing and energy and dose capability. The Genus Kestrel 750 has been designed to offer the best value for triple well and BILLI processing through enhanced outgassing control, higher energy range and superior chained implant capability.

References

1. Economic Report, Korea, vol. 12, no. 7, July 1997.
2. Nikkei Micro Devices, special feature, Nov. 1993.
3. Jeff Honeycutt, Micron Semiconductor Inc., presentation at the Genus 2nd Annual MeV Implant Seminar, July 1994.
4. Seiichi Mori, Toshiba Corp., presentation at the Genus 1st Annual MeV Implant Seminar, July 1993.
5. Fujii, et al., IEEE Journal of Solid State Circuits, vol. 24, no. 5, Oct. 1989.
6. J.K. Kim, LG Semicon, presentation at the Genus 5th Annual MeV Implant seminar, July 1997.
7. S. Dash, et al., IBM Corp., 1991 VLSI Symposium, June 1991.
8. K. Tsukamoto, Mitsubishi, Electric Corp., presentation at the Genus 1st annual MeV implant seminar, July 1993.
9. Roberto Bez, ST, presentation at the Genus 3rd annual MeV implant seminar, July 1995.
10. J. Borland, Genus Inc., Semicon Southwest 96 technical digest on 'Defect Engineering in Submicron Process Technologies,' Oct. 1996.
11. J. Kawski, et al., 'Cumulative Thin Film Stress and its Effect on Post Backgrind Wafer Shape,' Semicon Singapore Technical Symposium, 1992
12. J. Borland, Genus Inc., presentation at the Genus 2nd Annual MeV implant seminar, July 1994.

John O. Borland is vice president of strategic technology at Genus Inc. He has bachelor's and master's degrees in materials science from the Massachusetts Institute of Technology.

Phone: (978) 463-1500
Fax: (978) 462-0210