Application Report: Simulation Reduces Product Cycle Time

		At a Glance
	Cycle time, the time required to produce a finished wafer, must be kept to a minimum in order to meet demanding delivery lead times. Spreadsheet-based methods for examining the overall effects of alternative scheduling policies has its limits, and local optimization can have a negative effect on cycle time. A simulation-based software package is presented that can perform global optimization essentially in real time.

In today's era of extreme competition, the vendor who gets to market even a few weeks before another may grab the lion's share of the market. As product life cycles for semiconductors and the products in which they are used continue to be reduced, cycle time has become increasingly important. Cycle time is the total time for a wafer to be produced, from the time it enters the fab until it leaves. In turn, semiconductor purchasers are striving to reduce their time to market and are demanding semiconductor manufacturers to reduce delivery lead times. In many cases, the delivery lead time, which is primarily dependent on cycle time, becomes the most important factor in determining whether a semiconductor supplier wins or loses a particular order.

As a result, semiconductor manufacturers face the demands of reducing cycle time and time to market and reigning in the rising cost of fabrication while maintaining rigorous quality standards. Traditionally, the semiconductor industry has focused on increasing production volume by batching wafers through the machines in larger groups to increase throughput. However, this approach has the disadvantage of tending to increase cycle time.
In late 1995, Analog Devices was thrust into the center of this demand cycle. Management established a team charged with reducing cycle times. Consequently, the team set out to find a means of improving cycle times by optimizing scheduling policies rather than investing major amounts of capital in construction expenditures.

Compared to most discrete manufacturing industries, semiconductor wafer fabrication poses some unique planning and scheduling challenges. The large number of scheduling steps, frequently >250 per product, and the process repetition through the machines makes for an extremely complex scheduling task. Complexity is compounded by the intermixing of single-wafer and lot-based process operations, as well as batching of multiple lots that share process recipes and processing times.

Like other semiconductor companies, Analog Devices used spreadsheets to analytically evaluate the performance metrics of alternative scheduling policies. Spreadsheet models are easy to use and understand and are relatively inexpensive. However, they have inherent problems that oversimplify such things as linearity of work flow, behavior of fab equipment and true capacity.

Using simulation-based scheduling, cycle time is reduced without negative impact on throughput.

As a result, the operations staff began experimenting with simulation-based, finite-capacity scheduling and planning (FCS) software, which reportedly shows less than a 20% error in performance compared to a real-life manufacturing system. FCS software adds an important dimension, the dynamics of time-based material flow, that cannot be properly represented in a spreadsheet model. FCS systems allow the user to specify equipment, availability calendars, products, process routings, process times, support tooling, material handling systems, human operators and certification levels and numerous other constraints.

The operations staff required a simulation-based FCS package that offered the speed and flexibility to use the model in a real-time mode to actually run the fab. After evaluating several software packages, AutoSched FCS software from AutoSimulations Inc. (Bountiful, Utah) was chosen.

Operations engineers built a simulation model with AutoSched AP and used it as a test bed to evaluate the performance of the fab under a variety of different manufacturing policies. The simulation model showed that local optimization had a negative impact on cycle time.

Evaluating the effects of a large number of different rules, the staff was able to develop a general understanding of how the overall operations of the plant could be optimized. A key to its success was the institution of a software-based kanban, or pull system, featured in AutoSched, which drives the process production based upon critical ratio and process capabilities.

The kanban system was the key to optimizing the fab on a global basis. If one area had a problem, the other areas that fed work to it shifted to other products. This prevented the buildup of a large amount of work-in-process (WIP) inventory in front of the station that was down. This optimization resulted in a substantial cycle time reduction.

As a policy to improve cycle time was developed, engineers began to run parallel schedules in real time using an MES to update the facility model. AutoSched provided dispatch lists for each station making it easy for the fab to operate globally in accordance with the newly optimized policies.

As a result of implementing AutoSimulations' software, Analog Devices reduced average wafer fab cycle time with no reduction in throughput (see Figure). In addition, the reduction in cycle time variance has improved the reliability of delivery dates given to customers. The reduction in cycle time translates directly into crucial savings in time to market.

Sumer Johal is an operations research engineer at Analog Devices' Wilmington, Mass., fab. He has a BSEE as well as a MSCS/MSEE, both from the Massachusettes Institute of Technology.

Phone: (617) 489-7641
E-mail: sumer.johal@alum.mit.edu