Thermal Processing's Tool of Choice: Single-Wafer RTP or Fast Ramp Batch?

		At a Glance
	For years, single-wafer rapid thermal processors (RTPs) challenged diffusion and oxidation furnaces on the basis of lower thermal budget and precise control of the process ambient. Now, fast ramp batch furnaces are challenging RTP systems with shortened cycle times and their ability to combine two or more process steps. Furnace and RTP suppliers are battling over advanced dielectrics applications such as gate oxides, capacitor dielectrics and other oxidation processes. Where either technology can satisfy the process requirements, cost-of-ownership becomes the deciding factor.

In the joint development of the 256Mb DRAM process between Toshiba, Siemens and IBM, Toshiba claimed that the shortened process times enabled by Tokyo Electron Ltd.'s (TEL's) fast thermal processing system reduced raw process time for 0.25 µm (250 nm) diffusion processes by 30% relative to the 0.35 µm (350 nm) processes.² This signifies a dramatic improvement as raw process time -- including time to adjust process conditions, run test wafers and transfer wafers -- typically increases by 30% with each new device generation. Because of the reduction in process time, ability to speed process optimization and ability to combine furnace steps, Toshiba considers fast thermal processing 'essential for 0.25 µm design rules and beyond.'² Companies offering fast ramp batch furnaces include ASM (also in Phoenix, Ariz.), Eaton (Peabody, Mass.), Kokusai Electric (Nakano, Japan), SVG Thermco (San Jose, Calif.), Semitool (Kalispell, Mont.), Sizary (Migdal Tefen, Israel) and Tystar (Torrence, Calif.). In addition, GaSonics International (San Jose, Calif.) offers a small batch, fast ramp vertical processor, which operates at high pressures (to 25 atm) and is designed specifically to address oxidation applications.

Fast ramp furnaces (l) and RTP systems (r) compete for advanced dielectrics on the issues of temperature uniformity, temperature control, system throughput and cost-of-ownership. (Sources: TEL and STEAG AST)

Advanced thermal processing

As shown in Figure 1, conventional vertical furnaces will continue to be used for well drive-ins, field oxidation and gate oxidation of films thicker than ~100 According to Dr. Randhir Thakur, vice president of technology and R&D for AG Associates, approximately three years ago the landscape for RTP changed to include not only silicidation, nitridation and S/D anneals, but a wide variety of applications. Thakur explained, 'In the high-temperature (>850 regime, we saw implant damage anneal, polysilicon activation, S/D reoxidation and anneal, and dielectric densification and annealing.' He continued, 'The ambient became more important as applications be-gan using wet oxidation, NO, H₂, etc.'

The middle temperature range, where silicide and barrier films are processed (650-850, is now being applied to condition organometallic films deposited using CVD. Thakur explained that in the low-temperature regime (<650, applications are growing beyond common sintering and alloying processes to include curing processes for spin-on dielectrics, Ta₂O₅, BST and other films.

1. RTP and fast ramp batch furnaces compete for advanced dielectric applications.	2. From conventional furnace processing to fast ramp, cycle time for this gate oxide process is reduced by 75%. (Source: TEL)

3. Budget for a BF2 implant of 1020/cm3 is only a few seconds at 1000for a 0.25 µm device.

In front-end processing, gate oxidation is usually considered the most critical oxidation application, as required thicknesses shrink from 40-50 for the 0.25 µm generation to 30-40 for 0.18 µm devices and 20-30 for 0.15 µm (150 nm) devices. Gate oxide thickness control, according to the 1997 SIA National Technology Roadmap for Semiconductors, must be within plus/minus 4% of each of these thicknesses. Sluijk explained that fast ramp furnaces better than match the Roadmap's specifications. He commented, 'Although many observers believed that furnaces would not be able to produce 30 gates, the combination of fast ramp technology and nitrogen ambient control during loading, as offered in ASM's Advance 400i systems, leads to 30-40 oxide films with plus/minus 0.3% uniformity - with or without nitridation.'

TEL optimized its fast ramp gate oxidation process by combining a low-temperature loading process (300-400, fast ramp-up, gate oxidation and nitridation steps. (Fig. 2). By reducing native oxide growth during loading and by employing a fast ramp, the thickness control window for ultrathin oxides is increased during the actual oxidation step.

GaSonics' high-pressure processor is also capable of sequential processing -- performing native oxide removal, thin thermal oxidation, nitridation, reoxidation and post-nitridation annealing. Processing in the high-pressure system is typically in the 600-650range, with ramp-up rates of 30min and ramp-down rates of 10min. Typically, every atm of pressure will decrease the required process temperature by 30 Every atm of pressure also reduces the process time by 1/x.

Another example of the use of sequential processing in fast ramp batch furnaces is the formation of DRAM storage nodes. According to Bobby Shirai, FTPS marketing manager at TEL, a sequential nitride capacitor process is being used in the production lines of 6-10 DRAM manufacturers worldwide. In this process, wafers are heated to a high temperature (800-950 and exposed to NH₃ to both remove native oxide and grow a thin layer of thermal Si₃N₄. The wafers are then cooled to 650-700for nitride LPCVD. 'The in situ clean uses ammonia to remove native oxide, while also introducing nitrogen to the film, giving it a higher capacitance,' explained Dan Marks, business unit manager for diffusion and CVD systems, TEL in Austin, Texas. 'By pretreating with ammonia we get better nucleation, a smoother film and lower leakage current,' Marks said. Current-voltage and time-dependent dielectric breakdown characteristics for this film indicate that this dielectric will satisfy requirements for 1Gb DRAM manufacturing.²

Low-resistance contacts can also be fabricated by performing the above in situ clean and cooling to 600for polysilicon CVD. Film stacks of silicon nitride and TEOS oxides reduce raw process time from 8 hrs to 4 hrs, and a polysilicon/nitride/polysilicon stack can be performed in 6 hrs, compared with 10 hrs using separate furnaces.

In many oxidation applications, the case made for RTP is based on superior film quality or potentially better electrical results. In particular, RTP systems capable of plus/minus 2 degrees C uniformity and multipoint, multizone lamp control can effectively address requirements for ultrathin oxide growth. For example, in a recent study, STEAG AST showed that thin gate oxides (6 nm) can be nitrided in a low-temperature, low-pressure (100 mbar) process using NO gas, yielding properties at least equivalent to those obtained using N₂O nitridation, but with dramatically lower thermal budget.

4. SVG Thermco's double-tier carousel holds up to 16 cassettes in an ultraclean staging area.

A new application for rapid thermal oxidation is the first step in creating shallow trenches. Kelly Truman, global product manager of Applied Materials' RTP group, explained that 'rapid thermal oxidation (RTO) can be used to form the liner oxidation in shallow trenches, with better rounding at the edge of the trench.' According to Truman, the trench rounding is superior to the profiles provided by high-density plasma CVD systems or TEOS/ozone processes alone.

In one of Applied's RTO processes, an in situ steam oxidation at reduced pressure (10 Torr) can be used to increase oxidation rates, thereby becoming more competitive with furnace processing in terms of throughput and COO. At reduced pressure, the heated wafer acts as the reaction source to produce steam in situ. To produce both thin and thick oxides, growth rate is controlled by increasing the ratio of H₂:O₂ during the steam oxidation. For example, growth rates in excess of 150 min can be obtained at 105using 33% H₂ in an oxygen-rich ambient, compared with a growth rate of ~30 min for a dry oxidation at atmospheric pressure. Such thicker oxides are used as sacrificial oxides and also as trench lines as explained previously.

Applied addresses thin gate oxide RTO also using the steam oxidation process but with dilute concentration of H₂ (<2%). The reduced pressure environment improves uniformity at high temperatures, and contamination is reduced since the purity of the steam is only limited by the purity of the gases, H₂ and O₂, and not by external steam generation hardware. Gate oxidation of a 40 film is performed in only 30 sec. Integrated gate stacks are formed by performing RTO in one chamber of a cluster tool, followed by polysilicon deposition in a second chamber. Alternatively, gate oxidation can be followed with a rapid thermal nitridation step using, for instance, nitric oxide, forming an oxynitride gate dielectric. According to Truman, other emerging applications for oxides involve annealing and densification of Ta₂O₅, BST and other materials, to condense films, correct stoichiometry and optimize interfaces.

Thermal budget

Thermal budget refers to the allowed time-at-temperature for a given process step. It is based on the premise that by minimizing the time-at-temperature, diffusion of dopants in the silicon is minimized, and degradation of interfaces is also minimized. Engineers calculate thermal budget as simply the area underneath a time-temperature curve.

The primary technology driver for reduced thermal budget is the fabrication of shallow S/D junctions in ULSI devices. According to the 1997 Roadmap, these junctions will be only 36-72 nm deep for the 0.18 µm generation and 30-60 nm deep for 0.15 µm devices. RTP tools, which previously ramped at 75-100°C/sec, are being modified to ramp at 150-250°C/sec. According to Bob Hollands, vice president of sales and marketing, STEAG AST, for ultrashallow junction processes, customers are demanding very fast ramps (>200°C/sec) to reduce thermal budget and minimize transient enhanced diffusion (TED) effects. As shown in Figure 3, thermal budget to produce p⁺ scaled junction depths for 0.25 µm devices (assuming a concentration of 1 x 10²⁰ atoms/cm³ using BF₂) is only a few seconds at 1000°C and around 10 sec at 900°C.⁴ In addition, end-of-range damage plays an important role in shallow S/D properties. Because shallow damage anneals faster (see line in Figure 3 for annealing at 400 , end-of-range damage for shallow junctions must be as close to the silicon surface as possible.

Beyond the drive toward faster ramp rates, the formation of ultrashallow S/D junctions (<70 nm) with optimized electrical properties also depends on the process ambient. A recent joint development program between STEAG AST and Varian Ion Implant Systems (Gloucester, Mass.) compared anneals in N₂ with 50,000 ppm O₂; N₂ with 5% NH₃; N₂O; and N₂ or Ar ambients, with implants of 2.0 keV B⁺, 2.2 keV BF₂⁺, and 1.0 kV plasma doped (PLAD) wafers with a dose of 10¹⁵ atoms/cm². The group determined that annealing in the presence of oxygen produces the deepest junctions, while NH₃ produces substantial dopant loss and negatively affects dopant activation. The best results using single-step anneals were in N₂ or Ar ambient. The group then developed multistep anneals to optimize junction depth, retained dose, sheet resistance and remaining oxide thickness. Interestingly, the group found that the overall effect of fluorine in BF₂ implants is beneficial in the creation of ultrashallow junctions as it reduces junction depth and increases electrical activation.

5. AG Associates' Starfire RTP system, with open architecture Brooks Automation platform, is designed to provide 90 wafers/hr throughput.

It is important to note that recent research into thermal budget analysis revealed that a reduction in thermal budget (reduced time at temperature) does not always lead to better process results.⁵ The authors emphasized that thermal budget analyses must consider kinetic effects in thermal processing and the differences between the rate of the desired process relative to rate of the undesired process. Standard thermal budget calculations work best when the activation energy of the desired process is higher than that of the undesired (as in implant activation where the undesired process is dopant diffusion). In these cases, it is recommended that processes be performed at the highest temperature possible.⁵ Conversely, when the activation energy of the desired process is lower than that of the undesired process (as in oxidation where the undesired process is dopant diffusion in silicon), temperature should be kept as low as possible during processing. The group also found that fast ramping and cooling generally improved film quality.

COO

Although COO depends on many variables including system cost, labor cost, maintenance, equipment uptime, etc., it is largely dictated by throughput and yield. Even given the recent improvements in RTP system availability and throughput, fast ramp furnaces generally represent a significant throughput advantage over RTP systems. For instance, SVG Thermco's rapid vertical processor (carousel shown in Fig. 4) processes 100-200 wafer loads in 3-5 hrs, compared with 5-7 hrs in its conventional furnace. Uptime for this system is >93%. The smaller load size of fast ramp furnaces (25-100 wafers) also helps engineers overcome one of the drawbacks of traditional furnaces -- having to wait to process a full load (typically 200 wafers), in the interest of improving COO. Such long waits often limit cycle times in fabs. Fast ramp furnaces address this cycle time issue and further reduce cycle time by shortening raw process times by 50-70%. Depending on the manufacturer, fast ramping capability can be either retrofit to existing systems or is offered as an option on new furnaces.

Throughput gain of fast ramp batch furnaces is most advantageous when process times are short, as in the case of gate oxidation processes. When process times are longer, users still benefit from the shortened thermal cycle provided by fast ramp furnaces. However, because of the long time-at-temperature required to perform the process itself, the COO savings associated with transferring the process may not be significant enough to justify the purchase of a new furnace or the requalification of the process.

COO analyses comparing RTP and fast ramp are not straightforward as they must consider the application, including all steps (especially where film stacks are involved or thermal processing steps can be eliminated) and pre- and post-processing steps. Film stacks generally require an integrated platform such as the one shown in Figure 5.

R&D through production ramps

As chip manufacturers strive for shorter time-to-market and turnaround time, the rapid transfer of ULSI processes from R&D to production becomes increasingly valuable. RTP has long enjoyed the advantage that processes developed on RTP tools could quickly be transferred to manufacturing. Now, fast ramp batch furnaces can be used for both development and high-volume production, smoothing process transfers. 'One of the driving forces for development of the FTP (fast thermal process) system was to provide a quick turnaround tool for development,' explained Bob Soave, TEL's marketing manager. This approach eliminates the recharacterization step that many chip manufacturers perform when transferring a process developed on an RTP to a furnace platform.

References

1. L. Peters, 'Speeding the Transition to 0.18 µm,' Semiconductor International, Jan. 1998, p. 61.

2. K. Okumura, 'Fast Thermal Processing System (FTPS) Allows Consecutive Processing of Advanced Film Stacks While Reducing Process Development Cycle Time,' Nikkei Microdevices, Aug. 1997, p. 195.

3. P. Singer, 'Thermal Processing: The RTP Race Heats Up,' Semiconductor International, March 1996, p. 64.

4. C.Y. Chang and S.M. Sze, eds., ULSI Technology, McGraw-Hill Book Co., 1996.

5. E.G. Seebauer, R. Ditchfield, 'Fixing Hidden Problems with Thermal Budget,' Solid State Technology, Oct. 1997, p. 111.