All-Polymer Integrated Circuits

Plastics can mean low-cost processing of low-end devices.

Ruth DeJule, Associate Editor -- Semiconductor International, 4/1/1998

Plastics have become a topic of interest for low-end semiconductor devices. Recent progress in stability and processability has triggered their use in active elements of microelectronic and optoelectronic devices. Because of the easy processing afforded by these semiconductive polymers, for example, spin coating or silk-screen printing and minimal temperature hierarchy, this technology may prove to be a low-cost solution for low-end logic devices, LEDs and displays. The mechanical flexibility of these materials may open further applications. Recently, all-polymer integrated circuits (ICs) have been fabricated at Philips Research Laboratories (Eindhoven, the Netherlands) on flexible substrates that can sustain sharp bends and still maintain functionality.

Semiconducting polymers have been previously applied as the active component in metal-insulator field-effect transistors (MISFETs), and mobilities comparable to that of amorphous silicon have been obtained. However, with few exceptions, only the semiconducting component consisted of an organic material. Philips has developed and demonstrated all-polymer MISFETs for possible low-cost applications such as RFID transponders.

To fabricate the MISFETs, camphorsulfonic acid doped polyaniline (PANI) films are photochemically patterned. The PANI is dissolved in m-cresol, and a photoinitiator, 1-hydroxycyclohexylphenylketon, is added. The solution is then spin coated onto a polyimide foil substrate. In a nitrogen atmosphere, the film is exposed with DUV light through a photomask, whereupon the conducting PANI is reduced to non-conducting leucoemeraldine, increasing sheet resistance 10 orders of magnitude, from 10³ W/sq to more than 10¹³ W /sq. The conducting tracks are thus embedded in an otherwise insulating matrix. The topography of the exposed film with a typical thickness of 0.2 µm is less than 50 nm, making further planarization steps unnecessary.

1. Typical transistor characteristics of an all-polymer MISFET with a 2 µm long channel, 1 mm wide. Insert shows a schematic cross section of the device.

The conducting PANI tracks are used as interconnects and electrodes. A cross section of a device is shown schematically in the insert of Figure 1. Three photomasks are used in the process. The source and drain electrodes are defined in the bottom PANI layer. A 50 nm semiconducting polythienylenevinylene (PTV) layer is formed from a spun-on precursor film that is converted when heated in the presence of HCl. This PTV layer largely determines the electrical parameters of the transistor. A 250 nm thin polyvinylphenol (PVP) layer is then spin coated on top of the PTV film. This layer is used as the gate dielectric and as an insulating layer for the second layer of interconnect.

The nonexposed photoinitiator in the PANI films is removed through sublimation when heated. Dissolution of previous deposited films, however, must be prevented to maintain stack integration. The precursor PTV, insoluble in common organic solvents, is therefore dissolved in dichloromethane, a non-solvent. PVP dielectric, a photosensitive film, is cross-linked using hexamethoxymethylmelamine. Finally, DUV irradiation prevents degradation of the PTV semiconductor.

2. Micrograph of a discrete MISFET with channel length of 5 µm and width of 1 cm shows interdigitated source and drain electrodes, each 20 µm wide.

A top view of a discrete transistor (Fig. 2) shows interdigitated source and drain electrodes below the top common gate electrode. The defects seen in the micrography are due to dust particles, noted D. de Leeuw, research fellow at Philips. The channel length, in this case, is 5 µm, however channel lengths as small as 1 µm have been fabricated. The devices are operated under p-type accumulation mode enhancement. The normally ON devices are channel-enhanced at 0 V bias. The hysteresis is clockwise and may be due to charge trapping in the PVP gate dielectric. The charge carrier mobility is 10^-4 cm²/Vsec. Current saturation was clearly observed when the drain voltage was close to the gate voltage.

Combining several transistors into ICs requires the use of vertical interconnects (vias) between source and drain electrodes of respective discrete devices. A simple mechanical technique for the fabrication of vias was implemented. Pins are punched through overlapping contact pads defined in top and bottom electrode layers. When the pins are removed, an intermixing of electrode layers results. For large quantities of vias, a third mask step is used. Typical contact resistances are 3 kV per via. The most interesting application is the fabrication of ICs. Phillips processed a 15 bit programmable code generator with bit rates of 30 bits/sec. However, higher bit rates are expected because of the large improvement in mobilities of the semiconductor, de Leeuw noted. He said he anticipates that the devices can be used for practical applications in the near future.