Package Design Becomes Part of Chip Design
Package design starts to become part of the chip design.
John Baliga, Associate Editor -- Semiconductor International, 4/1/1998
Xynetix (Fishers, N.Y.) released version 1.4 of Encore BGA, a package design program that allows users to perform package design and analysis concurrently with IC design for single- and few-chip packages. According to the company, many IC companies are performing package design in-house, rather than outsourcing it to a packaging foundry, to optimize performance of the die-package combination.
The software package is designed to support wirebond, flip-chip and surface mount die attach technologies, and it accepts die and package data in industry-standard formats such as DIE, GDS-II, DXF and ASCII. Pin matrix creation and pin mapping procedures are performed automatically; very little work is required to make space for the die.
It treats wirebonds and their bondpads as physical entities as well as logical connections. PCB-based tools that treat wirebonds as trace segments or vias do not address their associated manufacturing issues, leaving them to be handled by a design engineer. When the positions of bond pads and wirebonds change, as in the case of a die shrink, this property can provide an advantage. Instead of having to "manually" readjust the design, the repositioning is done automatically, optimized using manufacturing rules rather than art-based design rules.
The software package continuously checks process rules and design rules specific to ball-grid arrays (BGAs) and chip scale packages (CSPs). Most PCB-based design programs use orthogonal routing, where traces run at 908 or 458 angles and are smoothed only after the layout is finished. This approach can be too limited for routing in a CSP. The Encore BGA package has an all-angle route editor that allows a designer to sketch a path and move other traces and vias as required.
Will Copper Interconnects Move Out on the Tiles?
Current die manufacturing technologies use up to five or six layers of interconnects to route signals to devices made on a 0.25 mm (250 nm) design rule. Depending on the design, the rules for the interconnect traces can be relaxed the higher up they are from the silicon surface. One of the tough challenges for upcoming design generations is to make more layers, with smaller design rules at the silicon surface and low-k dielectrics supporting them.
When looking at the difficulty of producing seven or eight metal layers on a chip, one may ask, "Do you need to put all the layers on the chip itself?" If the interconnects on the fifth level, for example, are spaced far enough apart to bond them to a package, why not put the last two or three interconnect layers in the package? Tessera (San Jose, Calif.) has been posing this question and proposing a solution that it refers to as "tiles."
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| Tessera's tile concept places some of the chip's interconnects in the package, rather than on the chip. |
It may be argued that this is similar to existing single-chip package designs. However, those designs are used to connect a complete semiconductor device to a circuit board. In the tile design, the device is completed with the addition of the tile, which is done at the wafer level.
