DFT Cuts Cost, Extends ATE Capabilities

Test costs are an eternal concern. Last year, the industry spent $4.9B on digital and SoC tester purchases. At least 60% of this investment was made to meet increased capacity requirements, according to Prime Research Group (Jacksonville, Fla.). The shift to 300 mm wafers — combined with the use of new fault models to detect DSM design failure mechanisms — will continue to drive the need for additional test capacity, furthering the rising cost of test. Other factors driving this area are the rising gate count, greater architecture complexity, and changing process technologies. Presently, scan testing is the fastest growing element of a device's total test time, typically representing more than 50% of the total test time.

The application of embedded deterministic test (EDT) enables massively parallel scan test operations, which result in ATE memory cost savings. (Source: Mentor Graphics)

Structural DFT techniques are used to automate the test pattern generation process and ensure high test quality. The industry-standard DFT method is based on internal scan and ATPG (automatic test pattern generation). This is a reliable and broadly applicable methodology that provides very high test coverage. In scan-base designs, sequential elements are serially connected in scan chains providing easy access to each sequential element. This significantly simplifies test pattern generation. ATPG tools generate patterns deterministically: Each pattern is designed to detect specific faults and satisfy constraints such as avoiding bus contention. ATPG tools support multiple models required to detect DSM defects.

To reduce test data volume, ATPG tools use software compression and optimization techniques to make test patterns as effective as possible, by detecting as many faults as possible. Increasingly, however, IC designs are reaching the point where test data volume is exceeding tester limits, requiring more efficient DFT approaches.

Mentor Graphics (Wilsonville, Ore.) has introduced a DFT technology it calls embedded deterministic test (EDT), which extends ATE capacity and reduces the cost of future ATE purchases. Its TestKompress product uses a compression technology that allows users to reduce ATE memory and time requirements for testing ASIC, IC and SoC designs by up to 10 times. Typically, scan testing represents more than 50% of the total test time, and Mentor's DFT technology can increase an ATE platform's throughput by up to 80%. This avoids the need for ATE memory upgrades, eliminates the use of test pattern reloads and avoids multiple-pass testing.

Test data compression results from the combination of embedding test logic at the interface between the scan chains and tester pins without changing the system logic, and new deterministic test pattern generation. The test logic is embedded at the interface between the scan chains and the tester pins, without changing the system logic. Also, the tight coupling of test logic and test pattern generation eliminates the need for test point insertions and "X"-bounding logic used with other DFT methods.

The new test technology is compatible with ATPG DFT flows. It uses the same scan DFT methods, script files and ATPG libraries, and supports all scan methodologies and fault models. The DFT technology also uses the same test vector formats and tester interfaces, enabling seamless and intuitive integration and adoption.