Flow Development Center to Shorten Technology Integration
-- Semiconductor International, 1/1/1999
Applied Materials Inc. (Santa Clara, Calif.) opened its Equipment and Process Integration Center (EPIC). The installation provides necessary equipment and processes to develop and test a completely integrated multi-level metal copper interconnect process before fab installation.
According to John Egermeier, director of the Process Sequence Integration Division at Applied, EPIC is a dedicated center that furnishes chipmakers with the capability of merging process integration and qualification tasks before any new equipment is put into the fab. This low-risk, economic off-site integration can cut capital costs by allowing equipment to be installed nearer the start of production and is expected to have significant positive impact on IC makers' competitive position and profitability in early stages of device production. The facility will incorporate Workstream DFS and Fab300 manufacturing execution systems (MES) software from Consilium. SMIF pods are used to transport wafers during processing to maintain a Class 1 cleanroom environment. EPIC is set up for 200 mm wafer structures but will expand to 300 mm.
The Center is designed to provide a fast turnaround on demonstration runs, enabling customers to evaluate all or part of their copper process flow and obtain electrical performance data. Process testing is performed using technologies including FTIR, Auger, SIMS, SPV and other tests. Device electrical performance is measured by a Hewlett-Packard 4071 DC test unit with a wafer reliability software option and an Electroglas 4090 prober with a high-temperature option.
EPIC is equipped with Applied's copper-based technologies, integrated to demonstrate a complete multi-level metal copper interconnect process flow. Other buildings house a DUV photolithography cell for wafer patterning plus a full complement of analytical and testing equipment for electrical performance verification. Presently, Applied is demonstrating, testing and prequalifying its integrated process module, the Copper Interconnect Equipment Set Solution (ESS).
Applied is collaborating with TestChip Technologies Inc. (Dallas) and Sandia Technologies (Albuquerque, N.M.) to offer test wafers with critical device structures and geometries, enabling customers to reduce start-up time by developing a process flow in parallel with circuit design. Since process integration typically takes months of engineering work after equipment is selected and installed, Applied expects the capability to perform pre-fab integration and testing of a completely integrated process module will reduce fab start-up time and shorten time to market for products. A reduction of six to nine months was mentioned.
'EPIC clearly increases the table stakes of the game,' said Ron Dornseif,
principal analyst at Dataquest (San Jose, Calif.). 'There aren't many companies
capable of putting together that kind of facility, program and level of support
for their customers. Those that would be able, do not appear to have the kind of
integrating strategy that Applied does, and are missing some key components.' he
added that there is a company that has a pilot line in Japan that is similar to
EPIC, but it does not perform full flow. He also said that alliances that other
major players had formed, although powerful, were not the same. 'They do not all
have the same products,' he said. 
