Samsung Simplifies Gigabit DRAM Design

Researchers from Samsung (Kyungki-Do, Korea) developed a new DRAM cell technology that merges storage node and memory cell contact processes to provide a simple, manufacturable process for 4 Gb DRAMs. The new cell scheme combines photolithography steps for the storage node and storage node contact, removing the shrinking alignment tolerance between the memory cell contact and storage poly. The new process eliminates the polysilicon etching step in addition to the buried contact lithography step, two 'bottlenecks of sub-150 nm DRAM cell processes,' according to Samsung. The researchers, Yoon-Soo Chun, Byung-Jun Park, Dong-Hwa Kwak, Yoo-Sang Hwang, Gi-Tae Jeong, Hong-Sik Jeong, Tae-Young Jung and Kinam Kim, summarized this new memory cell process at the latest IEDM Conference in December in San Francisco. This paper received the Best Paper Award in the Integrated Circuits Forum.

An important goal in Samsung's new process was to solve the problem of shrinking alignment tolerance between the storage node and contact, <20 nm for the 0.15 µm minimum feature size. Because the pattern sizes and alignment margin converge at the 0.12 µm minimum feature size, combination of the two processes is feasible. The structure is formed by deep oxide etching, followed by simultaneous deposition of the poly contact and storage node. This damascene structure further improves integrity of the doped poly structure, which at high aspect ratios is subject to undercutting caused by plasma charge-up during poly etch and subsequent tilting or falling of the storage node.

First, the bit line process is performed, followed by interlayer dielectric deposition and planarization by CMP or RIE assisted etch-back (see Figure). A thick oxide, which determines the height of the storage node (1 µm), is then deposited on top of the oxide/nitride stack. Then the storage node pattern is printed, and the oxide trench for the storage node is etched. The doped poly is deposited and then removed everywhere except the contact hole by CMP or RIE etch-back. Finally the thick oxide down to the nitride layer is removed by wet etch. The area of the storage node is further maximized by depositing and annealing a poly spacer to form hemispherical grain silicon (HSG). The Samsung researchers assessed that HSG increases the capacitor area by a factor of 1.8-2.3.

Fig. 1. A simple 4 Gb DRAM process combines the patterning of the storage node and memory cell contact, eliminating a lithography step as well as poly etch.

Theoretically, the maximum available area of a storage node is 8F², where F is minimum feature size. Typical storage node layout area in conventional stacked capacitors is 3F² in order to provide sufficient isolation space between storage nodes. At 0.15 µm feature size, storage area is 0.9675 µm², when the storage node height is 1 µm. In this process, measured capacitance of the 1 µm² capacitor with Ta₂O₅ dielectric (3 nm oxide equivalent) is 12.77 fF/cell at 1.2 V. With HSG, capacitance is 25fF/cell in 0.30 µm pitched 4 Gb DRAMs.

Samsung's alignment-tolerance-free process is simpler than present schemes, while providing extendibility in gigascale integration.