Introduction to Integrated Yield Analysis

Laura Peters, Senior Editor -- Semiconductor International, 1/1/1999

One of the highest leverage activities for improving profitability of manufacturing integrated circuits is probe yield improvement. Once a manufacturing process technology has been developed and released to production, the cost of manufacturing wafers is about the same whether wafer probe yield is high or low. Improving probe yields resulting in more good ICs per wafer increases revenue markedly, and most increased revenue (except packaging and final test costs) drops to the bottom line as profit.

For example, if the assumption is made that the average probe yield for a factory is 80%, and average revenue per wafer is $2000, improving yield to only 82% would increase the average revenue per wafer by $40. If factory output is 20,000 wafers per month, increased revenue would be $800,000 per month, or $9.6 million per year. If 20% of this goes into packaging and test costs, the increased yearly profit would be $7.68 million.

Fig. 1. Analytical procedures apportion yield loss to design, test, process, equipment and random defect problems.

Prices paid for ICs are typically much higher for chips that are among the first of their kind in the market. Therefore, higher yields early in the product life cycle have an even more dramatic effect on revenue and profit than the example given above. This emphasizes the need for methods to improve yields quickly, with as little data as possible and as early as possible in the development cycle.

Before probe yields can be improved, root causes of yield detractors must be understood. Also, methods must be available for starting new products with initially high yields. These requirements necessitate analysis techniques that are comprehensive, accurate, automated and efficient. The articles of this series, written by N. Atchison and R. Ross, will appear on Semiconductor International's website. They will describe in detail the analytical methods developed by the Texas Instruments SPG Yield Analysis Development Group.

Fig. 2. Example of two different yield learning rates.

The first article of this series presents an overview of the methods and software tools. These are organized from general to specific in the so-called IYM Triangle (Fig. 1). The IYM Triangle depicts a set of analytical procedures that apportion yield loss to various test, design, process, equipment and random defect problems. The IYM knowledge base allows for the prediction of the weekly average wafer sort yields prior to the actual sort week.

Subsequent articles in this series will provide detailed descriptions of the methods and software used to precisely calculate all appropriate yield losses for a given product. Figure 2 shows yield learning curves for two different process technologies. The rapid learning curve was achieved by utilizing tools described in this series of articles.