Catalyst Adds Control of HF Vapor Cleans

Ruth DeJule, Associate Editor -- Semiconductor International, 1/1/1999

Researchers from ASM International (Bilthoven, The Netherlands) and IMEC (Leuven, Belgium) have developed a vapor-phase clean using HF with an acetic acid catalyst that performs comparably to high-temperature bakes for epitaxial wafer preclean. This low-pressure, in- situ technique also shows promise as a replacement for HF-dips in TiSi₂ and Si₃N₄ applications.

Native oxide removal is necessary prior to CVD processes such as epitaxial Si and SeGe, TiSi₂ and Si₃N₄. Though Si epitaxy employs a high-temperature pre-bake for native oxide removal, in most instances, device structure and doping profiles limit thermal budgets. Thus HF-dip, an ex-situ process, is commonly used. However, this means potential reoxidation and recontamination during wafer transport to the CVD tool, making timing critical. Furthermore, because it is a wet process, there are drying issues, and quality variation of the HF solution requires monitoring to ensure consistent performance.

Vapor-phase oxide removal techniques are amenable to in-situ processing. The process ambient can readily be evacuated after vapor cleaning and replaced with an inert gas. Integration of a vapor etch into the CVD tool by means of a cluster environment is a straightforward extension of this concept, resolving time and recontamination issues. Because high-purity gases are used, reproducibility is ensured.

If anhydrous HF is exposed to the wafer, the initiation of the oxide vapor etch process will depend on the chemical condition of the oxide surface. The surface condition, in turn, is dependent on the history of the wafer, including storage time and ambient and thermal processes. A catalyst must therefore be added to the HF vapor during the initial phase of the etch process to provide a uniform and reproducible chemical surface condition, independent of the history of the wafer or the state of the etch reactor. The catalyst is intended to ensure that the etch rate is continuous, independent of the auto-catalytic nature of the etch process.

To evaluate the process, a stand-alone, single-wafer reactor, operating at low pressure, close to room temperature was used. HF vapor (4-12 scc) and an acetic acid catalyst (500-1500 Pa) were introduced sequentially with no gas flow during the etch. The onset of etching is immediate upon introduction of the gases, and the actual etch process in the isolated reactor takes 20-60 sec. Once etched, the reactor is evacuated, followed by several evacuation and backfill cycles and the wafer unloaded. Total process time is 2-4 min.

Fig. 1. Diodes with HF-acetic acid vapor pre cleans show comparable leakage currents to conventional methods.

The researchers used thermally oxidized 150 mm p-type <100> wafers as etch rate monitors and ellipsometry measurements to determine thickness on nine points across the wafer. Bare wafers with a thin chemical oxide were used for contact angle measurements to determine native/chemical oxide removal, and to verify etch selectivity, undoped, undensified TEOS oxide wafers were used. Comparisons were made to wafers cleaned with 2% HF in DI water for 30 sec.

The results were promising. Ten wafers processed within one hour under the same conditions indicated an average etched thickness of 3.7 nm, with wafer-to-wafer uniformities of ±0.1 nm and within-wafer uniformities <±0.2 nm. Particle addition for this process is within SIA Roadmap requirements, and no additional metal contamination was observed to detection limits of 1x10⁹ at/cm² using TXRF.

Finally, the HF-acetic acid etch technique was evaluated as a preclean for low-temperature expitaxial deposition by comparing it to HF-dip and high-temperature bake. Each of the three cleaning methods was used to remove native oxide from n-type wafers, then transferred ex-situ for an epitaxial growth of 1 µm p-type Si at 800°C, reduced pressure. Under these conditions, the quality of the epitaxial layer relies critically on the quality of the preclean. Diode structures, 300 x 300 µm, designed to electrically probe the substrate/epitaxial interface, were fabricated. A comparison of leakage currents (see Figure) indicates HF-acetic acid cleans to be comparable to high-temperature bakes and HF-dips, making this vapor clean technique a viable alternative to current technologies.