Metal Gates Could Replace Polysilicon Gates

Peter Singer, Editor-in-chief -- Semiconductor International, 1/1/1999

To overcome problems associated with polysilicon gates and thin gate oxides as devices are scaled to the 0.1 µm regime ­-- problems that include gate depletion, high gate resistance, boron penetration into the channel region and gate oxide tunnel leakage --­ it will probably be necessary to go to metal gates and high-k gate dielectrics.

At the International Electron Devices Meeting (IEDM), Dec. 6-11 in San Francisco, several sessions addressed metal gates and alternative gate dielectric materials. One report, from researchers at Toshiba Corp.'s Microelectronics Engineering Lab in Yokohama, Japan, described a damascene process they developed to produce metal gates. The researchers also showed that the high dielectric constant gate insulator (Ta₂O₅) is applicable in this process.

The Figure illustrates the fundamental process steps used in the damascene gate process. After shallow trench isolation (STI) formation, source/drain implants were performed, self-aligned to a dummy gate made of Si₃N₄/polysilicon films on a dummy gate oxide. A pre-metal dielectric film, SiO₂, was deposited by LPCVD and planarized by CMP in order to uncover the top surface of the dummy gates. Wet and dry etching were used to remove the dummy gate, and the gate groove was fabricated. After the dummy gate was removed, a gate oxide film, SiO₂ or Ta₂O₅, was newly grown in the groove. As a gate electrode, W/TiN or Al/TiN was deposited in the groove, and the gate electrode was formed by CMP.

The damascene metal gate transistor was found to show low gate sheet resistance, no gate depletion and 'drastic improvement' of gate oxide integrity, resulting in higher transistor performance.

Fig. 1. Gate stacks could soon be fabricated using this damascene process.

Company News   GaSonics International (San Jose, Calif.) received a follow-on order from Vitesse Semiconductor (Camarillo, Calif.) for its Performance Enhancement Platform (PEP) system. The system, configured with a photoresist removal chamber and a low-temperature clean chamber, will be installed in the Vitesse Pierre Lamond Wafer Fabrication Facility in Colorado Springs, Colo., the industry's first 6 in. Gallium Arsenide (GaAs) fab. Matheson Electronic Products Group (San Jose) opened a new 2800 ft2, hard-walled Class 100,000 cleanroom for final assembly, testing and inspection. The new cleanroom is an addition to Matheson's existing Class 1 cleanroom where all component assembly, welding, CT-1 certification as well as high-pressure decay and leak testing are performed. Mattson Technology (Fremont, Calif.) reports that Hitachi Nippon Steel Semiconductor Singapore Pte. Ltd. (HNS), a joint venture between Hitachi, Nippon Steel and the Singapore government, has placed an order for multiple Aspen RTP (rapid thermal processing) systems for use at its Singapore fabrication facility. PRI Automation Inc. (Billerica, Mass.) reached an agreement to acquire Promis Systems Corp. Ltd., a developer of Manufacturing Execution Systems (MES). The acquisition, which will be accounted for as a pooling of interests, is expected to be completed during the first quarter. SpeedFam International Inc. (Chandler, Ariz.) and Integrated Process Equipment Corp. (IPEC, San Jose), both suppliers of chemical mechanical planarization (CMP) systems, agreed to merge. The new entity will be called SpeedFam-IPEC. Varian Associates Inc. (Gloucester, Mass.) was awarded two orders from TECH Semiconductor for its Kestrel 650 high-energy implanter. The first system was shipped in December to TECH Semiconductor DRAM fabs in Singapore. The second system is scheduled to be shipped in the second quarter.