Is the 0.18 µm Node Just a Roadside Attraction?
Laura Peters, Senior Editor -- Semiconductor International, 1/1/1999
 The intense race to 0.13 µm and beyond makes the 0.18 µm technology node seem like a roadside attraction on the way to more interesting device generations.  |
Consistent with the industry's emphasis on productivity and COO, this article highlights 180 nm manufacturing challenges (Fig. 1). The Table summarizes possible solutions in each of the areas of lithography, wafer substrates, capacitor formation, trench isolation, gates, contacts, interlevel dielectrics (ILDs) and metalization.
Fig. 1| Table 1. DRAM Manufacturing Challenges | ||
| Module | Concerns | Possible actions |
| Lithography | Narrow process margin | Fully planarized process/mask CD control |
| KrF to ArF | Thin resist process | |
| Optical proximity effect | Optical proximity correction | |
| Substrate | Transfer to 300 mm wafer | Mass production in '99 |
| Few crystal originated pits | Epi/hydrogen annealed | |
| Increased performance/reduced process steps | SOI | |
| Gettering @ low-temperature process | Backside poly/Epi on P+ | |
| Trench capacitor | Increased storage capacitance | HDP deep trench etch, thin NO or pure SiN film, bottle-shaped deep trench |
| Buried plate formation | ||
| Deep trench poly fill and doping | Vapor phase doping | |
| Stress reduction | High temperature/thin oxidation | |
| Stacked capacitor | Step coverage/patterning | CVD BST/CVD Ru |
| Storage node Rc/peeling | Ru with oxide | |
| Endurance to H-termination and plasma damage | BEOL process optimization/barrier layer | |
| Trench deposition | Trench fill | HDP, high-temperature SAUSG |
| Stress reduction | High temperature/thin oxidation | |
| Gate | Dual gate | Oxynitride |
| Low Rs for gate contact | Poly/metal gate (eg. W/WN/poly) | |
| Low Rs for source drain | Co silicide | |
| Contact/pre-metal dielectric | Low-temperature process | W dual damascene |
| Void-less | HDP-PSG, TEOS-O3 PSG, SAUSG | |
| Self-aligned contact | Selective etch to SiN cap | |
| Inter-level dielectric | Low-k | FSG k = 3.3-3.7 |
| Water absorption | Siloxane SOG k = 2.6-2.8 | |
| High-temperature stability | Fluorocarbon polymer, PI, SG/polymer k <2.6 | |
| Mechanical stress | Air gap k = 1 | |
| Metalization | Low Rs | Cu wiring |
| Increase allowable current density | ||
| Patterning/gap fill | Damascene | |
Logic and memory highlights: At 180 nm, logic and memory requirements continue to diverge, while system-on-a-chip calls for common processes. Manufacturers of the most advanced microprocessors, DSP and communication devices lead the industry in device scaling and multilevel metalization schemes to maximize device speed and performance. Logic manufacturers are first to adopt new lithography platforms, copper interconnects, low-k dielectrics and CMP. DRAM devices drive etching and deposition of high-aspect-ratio trenches (>7:1) and use of high-k capacitor dielectrics and new capacitor plate materials to maximize charge storage per unit area.
150 nm features: To image 150 nm features (minimum in 180 nm logic designs), engineers use 248 nm scanners with 0.6 NA lenses, high-contrast resist, off-axis illumination (OAI) and/or phase shifting masks (PSMs). Engineers are using PSMs where economically feasible (high mask utilization), and OAI is used in the remaining critical-layer applications. PSM's return-on-investment (ROI) is critical, because device designs change so rapidly. 'Dielectric ARC films are increasingly being used to improve CD control, minimize coat related defects and eliminate substrate footing effects,' said Kevin Fairbairn, general manager of the PECVD Products Division of Applied Materials (Santa Clara, Calif.).
Lithography beyond 150 nm features will take one of two forms: extending 248 nm systems by increasing NA above 0.6 or making the transition to 193 nm lithography during 0.18 µm manufacturing. Dan Fleming, vice president of the lithography division of SVG Lithography Systems (San Jose, Calif.) claimed the 193 nm lens technology, scanner viability and resist technology are in place for early transitions. 'We have improved glass technology and infrastructure now, so people can make the move to 193 nm during second or third shrink 0.18 µm devices and be well positioned to springboard to 0.15 µm with a lithography technology that's already understood,' Fleming said.
The industry's slump puts unprecedented pressure on stepper and scanner manufacturers to improve throughput and COO. Integrating DUV scanners with the large installed base of i-line steppers raises COO, as steppers are ideally matched with steppers, and scanners with scanners. Users push for scanner throughputs above 100 wafers per hour, which simplifies integration of scanners with higher throughput track systems. Fleming explained the increasing importance of integration. 'With very narrow process windows you need to tighten the overall feedback loop and reduce effects of variation.' Gus Pinto, senior director of business development at KLA-Tencor (San Jose) explained. 'At least one of our customers is using wafer CD measurements to develop stepper-specific programs for a given mask to get the maximum benefit, the widest process window.'
Yield learning: Pinto explained how one inspection technology can dramatically speed a product's time to market and revenue generation (Fig. 2). 'Using voltage contrast inspection on the company's SEMSpec, an automated SEM-based inspection system, users rapidly isolate electrical problems, in some cases reducing design and development times by over an order of magnitude,' he said. 'Today, with companies having access to the exact same manufacturing process tools for rapid shrinks, you'd think they would become increasingly undifferentiated. We're seeing a somewhat contrary trend. By adopting critical inspection tools, some savvy customers are more rapidly bringing to market winning devices and processes, creating today's version of the technology 'haves and have-nots.'' With the increasing rapidity of device shrinks, Pinto stressed the management of non-yield-killing defects, which impact long-term device reliability.
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| Fig. 2. Correlating defect density with revenue growth. |
Defect learning on new processes and materials such as copper and low-k dielectrics will ultimately involve a coupling between wafer inspection tools information and process tools parameters, according to Dr. Andy Skumanich, senior technologist of Applied Materials' Process Diagnostics and Control Division. 'We've implemented such a methodology at certain customer sites,' he said. 'If, for example, a micro-scratch excursion is detected in a CMP tool, that tool is automatically shut down and corrective action implemented. In this way, the inspection tools not only assist in enhancing chip yield but also in increasing equipment utilization, since downtime is minimized.'
Yield may also be raised using new technologies for wafer backside contamination control. For example, SEZ America (Phoenix) offers planarization processes and chemistries that can help alleviate hot spot problems during lithography exposure, with a possible ROI after six months. The tool also proves instrumental in improving starting wafer flatness for advanced 200 and new 300 mm wafers. SEMATECH will soon address its effectiveness in backside wafer cleaning following copper deposition processes, a key requirement for copper tool integration with the rest of the fab.
Gate formation: 'Customers producing 0.18 µm devices currently require <10 nm CD bias and CD microloading and want chamber-to-chamber performance matching,' said Brad Hansen, general manager of Applied Materials' Silicon Etch Division. With the onset of sub-20 Å gate oxides, oxide integrity concerns also increase. 'Adjusting the process to perform well on the thin gate oxide with respect to selectivity may limit your capability to deliver good CD and profile performance with a satisfactory operating window. Endpoint technologies capable of switching to a highly selective overetch prior to exposing the gate oxide allow an additional degree of freedom by decoupling the poly main etch selectivity of the process recipe from the gate oxide integrity,' Hansen said.
Regarding throughput concerns, Dr. David Hemker, senior director of new product development at Lam Research Corp. (Fremont, Calif.) explained. 'During poly or gate etches, fluorine keeps the chamber clean, so depending on how you sequence the etch, you can extend the time between either dry or wet cleans by being smarter about the process chemistry you're using. As gates get thinner, post-poly-etch treatment also requires fast and efficient resist removal and cleaning processes to limit oxide loss and control profile.'
With increased use of thin nitride oxide and ONO gate dielectrics, metrology is increasingly challenged. 'With 100 angstrom ONO stacks, engineers want to measure the thickness of all three layers and refractive index of the top and middle layers, so that they know the composition, which is closely tied to transistor performance characteristics,' said George Collins, director of marketing for Rudolph Technologies (Flanders, N.J.). 'This is a really challenging application, and I don't know that anyone can provide the kind of repeatability that process engineers would like. We are combining ellipsometry with a DUV reflectometry measurement to monitor these films.'
Shallow trench isolation: At 180 nm, shallow and deep trench isolation processes replace LOCOS isolation in virtually all devices. Trench isolation processes consist of anisotropic silicon etch, thermal oxidation, oxide fill and often CMP. The thermally grown oxide sidewall eliminates any etch damage to the silicon lattice while rounding the corner of the silicon for stress relief and to prevent double humps on the IV curve. 'You need at least 100 angstroms of thermally grown oxide; many customers use up to 300 Å oxides to get good rounding,' said Dr. Wilbert Van den Hoek, group vice president of dielectrics at Novellus Systems Inc. (San Jose). Other STI oxide requirements include gap filling (>2.5:1), low mobile ion and metallic contamination for low leakage current and mechanical integrity for CMP compatibility. Dana Tribula, director of Applied Materials' HDP-CVD Product Group explained that STI drives HDP-CVD oxide technology. 'HDP-CVD is preferred due to its higher mechanical integrity relative to TEOS/ozone or LPCVD oxides and its lower cost, as an anneal step is eliminated,' she said.
A limiting factor in STI etch process productivity is chamber cleaning. 'Chemistries that eliminate deposition from chamber walls can extend mean wafers between cleans by five to 10 times, in addition to providing a 15% to 20% net throughput and uptime gain by eliminating dry cleans,' Hansen said. The etch process also benefits from etch-to-depth endpoint capability, eliminating repeatability problems associated with timed etches, Hansen added. (For more information on STI see SI's upcoming April feature.)
Shallow source/drains: With p and n junctions of minimal depth (sub-100 nm) and even shallower extensions (sub-50 nm), ultrashallow S/D junctions limit the thermal budget of the CMOS device. These junctions require high-current, low-energy implants and exceptional process integration with the RTP step. 'Subtle process variations can offset the depth of dopants by tens of nanometers, adversely affecting device performance and manufacturing yield,' said Dr. Israel Beinglass, chief technology officer of Applied Materials' Thermal Process and Implant Group. 'Fast ramp and spike anneal, while maintaining excellent temperature uniformity, are crucial to controlling ultrashallow junction formation.'
Residues following high-energy or high-current ion implant drive the need for more productive ashing processes. 'Our multi-step process enables rapid skin removal at low temperature,' said Asurhi Raghaven, CEO of GaSonics International (San Jose). 'Our tool's low-power RF and downstream microwave plasma modes maximize throughput and increase wafer cleanliness, while eliminating the possibility of plasma damage.'
Addressing thermal budget concerns following S/D formation, Ian Latchford, global product manager for PECVD at Applied Materials, explained that a single-wafer, low-temperature nitride deposition process for etch stop hardmask and spacer applications addresses junction diffusion issues associated with traditional batch nitride LPCVD processes. 'This 550-degree process is also compatible with new silicide technologies,' Latchford said.
Salicides and raised source/ drains: TiSi2-based self-aligned silicide (salicide) process capability is limited at smaller lateral dimensions, as TiSi2 films inadequately transform from the high- resistivity C49 phase (~70 mV-cm) to the low-resistivity C54 phase (~15 mV-cm). For this reason cobalt silicides with linewidth-independent resistivity of 15-18 mV-cm are starting to replace titanium silicides to achieve low-resistance contact to gate, source and drain regions. In CoSi2 formation, however, diode leakage issues must be minimized by: following Co deposition with RTA (600°C), depositing the cobalt at high temperature (>600°C) or implementing a short sputter etch clean after spacer etch and prior to cobalt deposition1. To increase thermal stability of CoSi2 films, LG Semicon (Cheongju-si, Korea) and Applied Materials Korea (Chunan-si Chungnam) recently demonstrated benefits of employing a titanium capping layer on the CoSi2 film2.
Texas Instruments (Dallas) proposed one way of extending TiSi2 technology1. By doping the silicon with molybdenum first, changing it to polysilicon and depositing the titanium, C54 phase TiSi2 films can be directly formed, bypassing the C49 phase.
Raised S/D structures can provide low contact resistance values of 1-2 V/sq relative to 5 V/sq on conventional devices1. Formed by depositing epitaxial silicon on source, drain and gate areas, raised S/Ds provide a larger area for silicidation, resulting in lower sheet resistance at a given gate length. Doug Meyer, executive scientist of ASM America (Phoenix) claimed several companies evaluated the feasibility of raised S/Ds at 180 nm, and many will adopt the technology at 150 nm.
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'Many companies will adopt raised source/drains at 150 nm. '
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Capacitors: 'Traditional oxide- and nitride-based capacitors are nearing the limits of their charge storage capacity at the current DRAM generation,' Beinglass said. 'New production equipment for tantalum pentoxide dielectric CVD addresses past problems with liquid delivery system reliability and equipment uptime to enable their use in production.' Platinum is a new DRAM capacitor plate material, though Pt electrodes have been used in ferroelectric RAM devices. Dr. Yan Ye, senior manager of metal etch technology development at Applied Materials explained that Pt electrodes pose special etch requirements due to the low volatility of Pt etch byproducts. 'Vertical profile and pattern fidelity requirements are difficult to meet. Our high-temperature processes address low volatility,' Ye said, adding that many hardmask schemes are being investigated to satisfy high-temperature and post-etch removal requirements.
Pre-metal oxide: Phosphorus-doped HDP-CVD oxides are replacing BPSG films for thermal budget reasons due to the high-temperature (850°C) reflow. Instead, engineers deposit HDP-CVD films at 600-650°C, a more reasonable temperature regime considering the effect on shallow source/drain junctions.
Barrier metals: Plasma PVD processes, commercially offered as Ionized Metal Plasma (IMP) by Applied Materials or Hollow Cathode Magnetron processes by Novellus, extend the applicability of PVD technology for Ti/TiN and Al deposition. Ti/TiN barriers are getting thinner: < 100 Å total stack thickness for 180 nm devices. New TiN CVD provides high-aspect ratio contact barriers in high-volume 1 Gb DRAM processes with scalability to >8:1 aspect ratio for 130 nm devices. In addition, in-situ silicidation at the 600-650°C process temperature eliminates the RTP step, according to Girish Dixit, director of advanced metal technology at Applied Materials. 'TiN CVD provides the potential as a plug fill material itself, offering conformal coverage and low stress,' Dixit said.
'Process monitoring of 100 nm barrier layers requires new technology to determine whether a bilayer exists or if you simply have a graded film,' Collins said. 'If the barrier properties are present at a given thickness, engineers then need to determine if they still exist at half that thickness to meet next-generation requirements.' Four-point probes were traditionally used to monitor these films, but inconsistent results led to the evaluation of alternative inspection methods. 'Picosecond ultrasonic technology has been shown to provide one option; it is fast, non-destructive and correlates with thicknesses determined by cross-section TEM, XRF, RBS and other traditional analyses,' he said.
Aluminum interconnects: Plasma PVD systems extend Al sputtering capability and represent the next step following standard PVD and Al reflow in DRAM devices. 'In Al etch, issues such as loss of profile control, notching and device damage become more serious, as metal interconnect sizes approach 0.13 µm,' said Dr. Peter Loewenhardt, senior manager of metal etch technology at Applied Materials. 'Plasma uniformity is only one requirement for low-damage process performance in this small feature size regime, with parameters such as electron temperature and energy distribution function shapes also playing a critical role,' he said. 'Overcoming the compromise between residue control and resist selectivity is paramount in aluminum etch, especially as the resist thickness shrinks due to depth-of-focus considerations.' GaSonics' Raghaven explained that changes in plasma etch technology cause changes in post-metal etch and post-via etch resist removal. 'We can reduce the number of process steps and lower costs by integrating post-etch photoresist and residue removal steps into our platforms,' Raghaven said.
ILDs: The majority of multilevel logic devices use HDP-CVD oxide ILDs, replacing SACVD, dep/etch/dep and SOG solutions. Many stacked capacitor 0.18 µm DRAM designs use two levels of aluminum with spin-on glass, silane-based PECVD and/or TEOS/ozone-based ILDs, while trench capacitor designs often have three Al levels, using CMP and PECVD or HDP-CVD oxide. 'In a two-layer metal structure, you get away with using a thin liner, SOG and thin TEOS cap, effectively a 0.5 µm solution,' Van den Hoek said. 'The people using CMP and HDP-CVD technologies today will have an easier transition to 0.13 µm technology.'
Advanced dielectric etching often calls for use of HDP sources. However, depending on the application, Hemker explained that medium density sources may also meet advanced process requirements, while minimizing frequency of chamber cleans, as HDP etches typically require an in-situ clean after each processed wafer. Medium density sources also reduce potential for etch damage.
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'To minimize the risk of copper integration, some companies are pursuing a dual strategy.'
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Low-k dielectrics: A variety of CVD and spin-on, low-k materials compete for use in production devices3. Material choice largely depends on performance, ease of integration, overall COO and extendability to future device generations. For 0.18 and even some 0.25 µm logic processes, companies are using inorganic low-k dielectrics, predominantly fluorinated oxide (FSG), but also hydrogen silsesquioxane (HSQ). However, significant integration challenges and small relative gains in device speed of 1% to 5% convinced some chip manufacturers to avoid low-k altogether at 0.18 µm. Capacitance reduction and device speed gains depend on the integration scheme and device layout. IBM recently showed that FSG offers a 14% reduction in capacitance, reduced to 12% reduction with a capping layer4. 'For the 2% penalty in capacitance reduction, you buy production worthiness and reliability,' Van den Hoek said.
Applied Materials' Dr. Farhad Moghadam, vice president and general manager of Emerging Dielectric CVD Technologies, sees FSG as a first-generation low-k solution, followed by an ultralow-k CVD film. 'Our inorganic, silicon-based Black Diamond process (k = 2.7) can be integrated into a dual-damascene process flow with dielectric etch, metal deposition and CMP processes at a cost comparable to traditional TEOS or silane-based dielectric films.'
Copper interconnects: To minimize risk of copper integration, some companies are considering a 0.18 µm dual strategy, i.e., running aluminum-based 0.18 µm processes in production first, using damascene copper on limited-volume products. 'Some customers will gradually phase in copper interconnects, as they acquire integration expertise to bring yield to acceptable levels,' said Dr. Ashish Asthana, senior product manager at Lam Research. 'In such schemes, the lower level local interconnects use aluminum subtractive etching with copper global interconnects. Some high-performance logic or microprocessor makers will make the jump exclusively into Cu dual damascene, putting devices with five or six levels of Cu into production in 1999. At the other end of the spectrum are DRAM and some ASIC makers who will stay with Al metalization until 0.13 µm.'
Tantalum and/or TaN barriers are currently deposited using plasma PVD systems, offering extendability to future generations. Applied Materials offers an integrated process platform performing pre-clean, IMP Ta/TaN and IMP Cu seed layer deposition. The company is also developing Cu-CVD processes that may be required to increase Cu sidewall thickness prior to electroplating. Applied uses a counter-bore damascene architecture consisting of ~12 steps, that 'gives us easier integration on the via and guarantees better metal contact area than other process flows we evaluated,' said Dan Carl, general manager of Applied's Copper Division. He estimated integrated, fully-characterized platforms will save the customer up to six months development time.
Reliability and productivity are key considerations for damascene etching, explained Mike Rice, senior director of engineering and technology at Applied Materials. 'The capability to provide high-rate etching of the primary dielectric film, followed by a resist removal and nitride barrier removal, all in-situ, can result in a highly productive process step,' he said. 'Etch reactors with a wide operating window, especially in terms of pressure and energy, provide the greatest capability in this area.'
Final passivation: Final passivation, the stress buffer for the packaged device, also planarizes the wafer following final metalization. As engineers implement more layers of HDP-CVD for ILD, the thickness requirement of the final PECVD nitride passivation layer actually relaxes. 'Since HDP provides 45-degree features, you get 100% step coverage with your PECVD layer,' Van den Hoek said.
300 mm Update: Originally slated for early 1999 introduction with 0.25 µm production processes, it now appears that 300 mm will be more coincident with 0.13 µm devices in 2001. The delay allows more time to scrutinize 300 mm costs. 'Only the process chamber changes at 300 mm, while keeping a common user interface, operating system and software,' Raghaven said. Hemker added that 300 mm processes require tighter tool-to-tool replication of processes through modeling and characterization, upgradeable platforms and a flexible control framework for plug-and-play sensor integration. 'Such standard platforms are essential if we're going to eliminate customer specials, the feature additions that really increase cost in this industry,' he said. 
References
- J. Kittl, et. al., 'Salicides: Challenges and Solutions for Future CMOS Technologies,' Future Fab International, Issue 5.
- D.K. Sohn, et. al., 'High Thermal Stability and Low Junction Leakage Current of Ti Capped Co Salicide and its Feasibility for High Thermal Budget CMOS Devices,' Proceedings of IEDM, December 1998.
- L. Peters, 'Pursuing the Perfect Low-k Dielectric ,' Semiconductor International, September 1998, p. 64.
- D.S. Armbrust, et. al., 'Integration of HDPCVD for 0.25 µm CMOS Technology,' DUMIC Conf., 1998, p. 67.
