Copper Moves CMP to Center Stage
Alexander E. Braun, Senior Editor -- Semiconductor International, 12/1/1999
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At a Glance | | |
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As IC designs progress and six-metal-layer devices with three or more photomask levels loom on the horizon, CMP must perform its time-honored function at increasingly higher sophistication and precision levels. Materials such as copper and noble metals present new challenges and opportunities for the old craft. (Fig. 1)
'CMP's the fab's 'ugly duckling,' ' said Duncan Dobson, vice president of sales and marketing for Strasbaugh (San Luis Obispo, Calif.). 'Few fab managers like it. It doesn't fit their view of the fab environment. If they could, I think they'd pay to be rid of it.'
'This year I've been amazed by the turmoil and dynamics within the CMP post-clean field,' said Bob Small, R&D director for EKC Technology (Hayward, Calif.). 'I'd thought that by now it would have begun to settle, but first-generation chemistries are evolving, and the pressure to move on to tungsten and obviously to copper is increasing faster than expected.'
'Copper is happening, but good process control and capability for oxide and metals like tungsten and aluminum is needed,' pointed out Michael Olesen, senior member of the technical staff at Verteq, Inc. (Santa Ana, Calif.). 'The thinking was everything would focus on copper and the rest vanish, but it's not going away, and while the future may be copper's, the rest of us are still going strong with traditional materials.'
Rob Davenport, global product marketing director, CMP Division, Applied Materials (Santa Clara, Calif.), views tungsten CMP as an upward trend. 'It's replacing tungsten etchback for advanced applications, especially at 0.25 and 0.18 µm. Forecast data support this, showing that CMP's tungsten market share has grown to almost 30% of the total.'
'As features shrink, so will the industry's patience with CMP-induced defects,' said Frank Kaufman, a CMP Fellow at Cabot Microelectronics Materials Division (Aurora, Ill.). 'Meeting volume manufacturing process yield and device reliability targets will become increasingly difficult. Improvements in process consumables are already being delivered in response to this need. Further improvements are needed.'
Tough CMP issues
From a slurry and manufacturing perspective, Kevin Witt, Interconnect Program manager for Rodel (Phoenix), sees CMP maturing. 'We're reaching a critical mass of scientific understanding that's taking us beyond empirical approaches. Instrumentation now looks into what was considered an abrasive science 'black box,' ' Witt said. 'This is evident in new copper slurries. With few exceptions, supplier-developed slurries are working better than those developed by the customer. This is a reversal from tungsten slurry development, where customers' slurries were better for years after commercialization than supplier-made slurries.'
Witt sees consumable variability drivers as crucial. 'Processes are tolerant of incoming variation, but as performance requirements increase, tolerance drops,' he said. 'We're running out of margins and having to tackle first-principle interactions. Modeling shows where the issues are, but not the solutions.'
Available tooling is unready. 'Automation and sensors (endpoint, for example) must improve,' said Witt. 'Metrology is a problem, and linking information gained in-line at the fab level with data from the slurry or pad manufacturer is complicated. There is still great weakness in material properties as leading indicators of successful polishing.'
Avner Sharon, product marketing manager at Nova Measuring Instruments Ltd. (Rehovoth, Israel), sees a major undertaking in developing the capability to measure dishing, erosion and residues directly on dual-damascene structures by using Integrated Thickness Monitoring (ITM) systems. 'These as well as stand-alone tools today measure layer thickness on solid areas -- that is, on homogeneous flat layer stacks,' said Sharon. 'Copper dual-damascene requires that thickness and thickness loss be measured directly on dual-damascene structures. CMP's effects there are significantly different than on solid structures.' Sharon added that dishing and local erosion on dual-damascene are more pronounced than on solid oxide sites. 'Residue measurement and detection is important because residues can ruin the product,' he said.
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Fig. 1 CMP has become a hub process in today's fab,
driven to higher sophistication and precision by shrinking architectures,
new low-k materials, and the introduction of copper and noble metals.
(Source: EKC) |
Adapting CMP to copper
Although copper's growth does not surprise Applied's Davenport, he points at incomplete solutions. 'There are two basic CMP approaches: one uses a medium- to high-selectivity slurry, while the other employs a low-selectivity slurry. Both have disadvantages. High-selectivity slurries still dish and erode the wafer, leading to unsatisfactory planarity,' he said. 'Fabs implementing it must do an oxide CMP step for at least every other device layer, adding complexity.' Davenport recalled how, when copper damascene costs were first calculated, it was assumed that oxide CMP of the ILDs would not be necessary. Currently that is possible only with the low-selectivity approach, which provides a very planar surface, eliminating the intermediate oxide polish. However, it is costlier due to higher copper loss, requiring it to start with more copper and oxide.
With shallow trench isolation (STI), the trend is toward direct polish, meaning no reverse masking or excessive use of dummy features. This justifies device production costs. 'Most CMP suppliers are working on it,' said Davenport, adding that it is doable. Applied has demonstrated a very planar process with minimal dishing, capable of con trolling isolated features.
Rod Kistler, senior director of CMP and cleans process technology at Lam Research (Fremont, Calif.), said Lam's Teres integrated CMP system, which uses conventional oxide process slurries for direct-polish STI, is being used by AMD at its Austin, Texas, Fab 25.
COO factors
As CMP applications grow, cost-of-ownership (COO) increases in importance. A typical DRAM requires five to seven CMP steps, while a prototypical logic device can have up to 14. Consumables determine most of CMP's cost; thus the focus on reducing slurry usage, lower-cost pads, pad life extension, etc. The fixed abrasive concept is attractive precisely because it eliminates a key process variable (slurry), contributing to process stability, up-time and reduced engineering oversight. This, along with its planarization efficiency, might eliminate additional steps such as double-mask etch-back in STI, reducing process COO. Although the actual consumables are not much cheaper than slurry-based ones, the abrasive process' inherent benefits can help lower process costs. In two years, at least 15% of the total CMP market is expected to migrate to fixed abrasives.
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Fig. 2 Polysilicon CMP processes are becoming more
important, particularly with the introduction of high-performance
sub-0.18mm capacitor and
transistor device designs for next-generation DRAMs. Applied Materials'
Mirra Polysilicon CMP system is targeted to meet these requirements.
(Source: Applied Materials) |
Scratching, a traditional obstacle to fixed abrasives, is being minimized as application knowledge increases. Tight particle control of the cerium and alumina used will be key to their successful application. So far, cleaning has not been a problem to extending this technology's application.
Other CMP key drivers, especially with DRAMs, are the polishes close to the transistor surface. Fabs want to avoid expensive steppers and stay with I-line technology. Even with phase shifting, however, a very planar surface is required. Conventional techniques for poly polishing and formation as a self-aligned contact do not work well. To use cheaper lithography methods it is necessary to go to CMP of poly for self-aligned contacts and some capacitor plates. Some of the most critical polishes now are STI and copper; they are also the toughest.
Tool integration
Although many longtime users are satisfied with stand-alone CMP (meaning dry in/wet out), copper will force most everybody to integrated dry in/dry out. Over the next five years, nightfall will come to dry in/wet out technology as fabs embrace the cycle time benefits and operator interface minimization that result from tool integration.
CMP is probably the fab's most metrology-intensive process. Many monitor each CMP lot; others monitor it twice (premeasurement and postmeasurement), and thrice if a rework is done. Metrology-associated downtime can account for up to 50% of tools' time. Integrated and in situ metrology are becoming critical to throughput. Applied has integrated the Nova and NanoMetrics in-line thickness monitoring systems to its system, and has closed-loop control capabilities as well. (Fig. 2)
Damascene's benefits are not limited to copper. 'It'll become necessary to polish exotic metals for advanced capacitor applications,' said Applied's Davenport. Designers are considering damascene gates, where the poly is polished at gate level in a damascene format. 'As more devices are created in the damascene manner with different materials, CMP will become increasingly necessary,' he added.
Consumables and profits
Consumable variability and its profit impact are a misunderstood area of CMP. Pads may vary from lot to lot, affecting performance, rate, rework and even scratching. Slurry also may vary and have settling issues. Filter maintenance and replacement is another issue. Some CMP users are naive about consumables. They may have worked on CVD, where the gas comes to the tool and is always there, or with PVD, where targets are consistent. With CMP they discover things are not as mature and controlled. CMP veterans know continuous effort is required to maintain consistency. Some even produce their own slurry.
Applied recently released a drop-in polysilicon process focused on next-generation needs, which operates on its Mirra Mesa system. While poly is being done for trench capacitors, this application addresses more stringent requirements.
There can be up to two poly CMP layers in advanced logic DRAMs. When both the transistor level and the capacitor formation are considered, this can rise to four. The Applied poly process provides the capability to create new device features and get better electrical performance. Its multiplatten architecture provides precise endpoint control, with minimum dishing, as it polishes through the poly and stops on oxide. The proprietary process uses multiple steps and slurries, and the cleaner is integrated within the platform.
Poly CMP has an oxide cap layer on top of the poly, making the process more difficult. It must go through the cap layer and polish the poly for the best uniformity; otherwise islands result. Additionally, it is necessary to ensure that -- whether tungsten plug or copper damascene -- the process halts at the stop layer, minimizing plug and trench loss. A nitride stop layer sometimes is used for that purpose.
The system may eliminate the nitride stop layer, said Applied's Davenport. 'It starts with an oxide breakthrough polish, using a non-selective slurry for oxide and poly suited for oxide removal. Next, it goes to a poly main polish, using a high-selectivity slurry that allows high removal rate. On the second platten the poly main polish is endpointed, and the system switches to an overpolish step that uses the non-selective slurry again. Finally, the third platten does buffing and defect removal, as well as a post-CMP oxidation step.' The system has demonstrated an average removal rate of nearly 4,500 Å/min, resulting in within-wafer non-uniformities of <2%.
CMP in the spotlight
CMP is mutating from a corrective rework process into an enabling technology. 'Before, CMP was used to correct failures in depositing layers in a smooth planar fashion,' said John Boyd, director of process technology for Strasbaugh. 'Now it's part of the circuit creation itself, a process hub.'
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Fig.
3 Comparison of thickness uniformity results for an SiOx/Si and
SiOx/TiNx/Al/Si patterned wafer, obtained using a small spot system with
patterned recognition (top) and a large spot system without patterned
recognition (bottom). The slight differences at the edge are due to the
fact that the mesurements were made on every die and there were
essentially none at the edges. (Source:
n&k) |
Strasbaugh believes a major challenge facing CMP is producing a successful, damascene copper technology that is acceptable in a production fab environment. 'Most pilot line production houses use their own 'soup' formulations -- nothing commercially available,' said Boyd. This must change for full-volume production. 'Slurry suppliers will eventually provide a well-controlled, viable solution,' he predicted.
The move to tungsten and copper is very demanding, and not helped by the fact
that tool sets also are evolving. 'We've seen new disciplines such as the Web
and linear technologies come in,' said
There is uncertainty over which solution to choose. 'Low-k's an example,' said Small. 'There's no winner. We must work with everything.' Even well-established, standard process oxide and tungsten slurries are being re-evaluated. With new processes, such as tungsten damascene, in which traditional tungsten slurries may no longer be sufficient, there is widespread interest in new slurries.
Cleaning and metrology choices
When cleaning is integrated to the CMP process, COO rises. Because of how COO is measured, yield must be calculated as part of it. Fabs are talking about 0.08 µm-level defects -- a significant shift from those being me asured a year ago-- becoming yield impactors. By its very nature, CMP casts large and small particles on the wafer and grinds them in. These become more difficult to remove as they, too, shrink in size.
Companies like Strasbaugh are researching alternative non-contact cleaning methods such as megasonics. Megasonics has been moderately successful, but it is not simple to apply to 0.08 µm particles -- it requires expensive metrology, different approaches to maintaining process cleanliness when coming out of the tool, and an integrated cleaning system.
Probably the biggest metrology challenge facing CMP is shifting to real-time control. Over the years, many processes have been clustered, and there is a move to use commercially available, on-board, in-line metrology. However, it is one thing to do in-line metrology and a different matter to do in situ, real-time metrology on the tool, coupled to real-time, closed-loop controls.
Most CMP in-line metrology has been related to film thickness. Defectivity is becoming a consideration -- how to deal with it without requiring the fab to process a couple of lots of wafers, take them off, and then determine defectivity issues. This must come further up in the sequence to avoid processing costly wafers without knowing the defect levels. Patterned wafers probably will be used, and it will be a complicated metrology issue. Endpoint techniques, automated process control and a tie-in to a fab host-type setting will be needed.
CMP characterization, in-line or through water, involves micro-spot size reflectivity measurements requiring pattern recognition. This can be costly and time-consuming, and at times the pattern may be misinterpreted. Inaccuracies can occur when these techniques rely on preset, not measured, values of n and k in thickness uniformity determination. n&k Technology (Santa Clara, Calif.) has developed a proprietary technique for characterizing patterned CMP wafers. It involves reflectance measurements over an area that is large relative to the size of the pattern or features. (Fig. 3) The method provides accurate mapping of thickness uniformity for the entire wafer without the need for patterned recognition, through simultaneous determination of film thickness and n and k spectra (190 to 1000 nm).
Strasbaugh is developing a third-generation technology, encompassing two approaches. One is a currently available rotating platten architecture using advanced consumables. The other uses non-conventional architecture and consumables, and company officials are not yet prepared to discuss it.
Strasbaugh is betting on integrated cleaning within the CMP system's footprint. 'Non-contact cleaning will be adopted for newer applications,' said Boyd. 'Fewer moving parts mean higher reliability, lower consumable use (no brushes) and lower COO.' Early in 2000, Strasbaugh will introduce its Symphony II CMP system, integrated with the Verteq Goldfinger cleaner, using a redesigned carrier, as well as oxide and metal endpoint detection and automated process control.
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Fig. 4 In 2- and 3-step approaches for copper
dual-damascene, slurries are developed for purposes such as removing the
copper layer from the barrier. The 3-step process uses another slurry to
remove the barrier layer to the copper from the underlying dielectric, and
a third to reduce dishing and erosion. (Source:
Strasbaugh) |
'When running multiple processes in a fab, CMP is used for oxide, metals -- such as tungsten and polysilicon -- and others,' said Strasbaugh's Dobson. 'Having a platform capable of doing it all well is advantageous. It means no different training for different tools, and common stocks, spares and consumable sets.'
There are several avenues to copper CMP. One is a one-step approach where a single slurry removes the copper barrier and underlying dielectric. It has not worked well in the past, so slurries have been developed for application-specific purposes such as removing the copper layer selectively from the barrier. There was a slurry that selectively removed the barrier layer to the copper from the underlying dielectric. Then another was used to reduce dishing and erosion, making it a three-step process. Variants are being considered, where copper is removed partly and a non-selective slurry is used to simultaneously remove copper, barrier and the underlying dielectric. (Fig. 4)
The Strasbaugh approach decouples those steps. If one set of consumables needs changing, the whole process does not need redevelopment -- only the affected steps. In the two-step process, slurries designed to remove co pper barrier and oxide on the second step will not be useful with a low-k dielectric. 'There'll have to be process reoptimization or reformulation,' said Dobson. If individual process steps can be decoupled, it becomes possible to customize a slurry for that step, and not try to find a compromise for all three.
Going beyond scrubbing
'Scrubbing is the industry's traditional methodology -- double-side scrubbing, mechanical removal of debris from the surface,' said Verteq's Olesen. 'It works effectively, but we're seeing issues with metal stacks where some topography remains such as tungsten keyholes, alignment marks -- areas where slurries can escape scrubbing techniques. Etches and backsides are also a problem.' Verteq is relying on megasonics to perhaps eliminate scrubbers. 'We've seen companies such as Applied and Strasbaugh come into the arena,' said Olesen. 'This indicates they think scrubbers are insufficient.'
Verteq has two megasonics applications. The VcS is batch-process-oriented, providing a 200-wph throughput. 'It's for large applications where throughput is an issue and they're trying to couple multiple polisher machines to the cleaning solution,' explained Olesen. The other Verteq approach is its Goldfinger platform, a single-wafer-oriented product for integrated solutions. If the fab wants a polisher that puts out dry wafers -- dry in/dry out applications -- the platform is a good fit.
Olesen is quick to add that while the system's other capabilities exceed those of scrubbers, its particle removal capability -- although equal to scrubbers -- does not necessarily surpass them. 'If on a planar wafer you're down to the last 10 particles with a scrubber, megasonics will also be at 10 provided those particles aren't cleanable, which is typically the case.'
Low-k materials are hard to clean; some are easily damaged. 'We've developed 'soft' megasonics applications that, because of the curvature of the quartz rod, the energy propagates from it at 180°. So it isn't focused on one small spot like most other megasonics approaches, causing structure damage such as line lifting,' said Olesen. According to Verteq, more focused megasonics approaches can increase damage potential to delicate low-k materials.
Low-k challenges
Lam's Kistler sees low-k as a challenge. 'There's an emergence of organic
silica glass materials,
The move to next-generation low-k, where dielectric constants of 2.0 are sought, is an obstacle. 'Increasingly, these materials have a porous structure,' said Kistler, 'posing problems. One of them is the films' mechanical strength. Linear polishing technology enables users to operate at low down forces in high linear speeds and accommodate those materials' fragile nature.'
The issue, according to Lam, is in the post-CMP cleaning process of these porous low-k materials. Within the CMP environment, the wafer substrate is exposed to a variety of chemicals and abrasive particles during polishing and cleaning. Chemistry and particles are trapped in these pores, becoming difficult to remove. 'We're pursuing several options to clean and dry the porous materials,' said Kistler.
Many technologies, processes, films and equipment sets will appear in the
relatively near future. As with all environments with uncertain futures, it is
important for fabs to maintain flexibility. During this transition period,
success will come to those who allow themselves maneuvering room.
For more
information:
| Applied Materials | www.appliedmaterials.com |
| Cabot | www.cabot-corp.com |
| www.ektech.com | |
| Lam Research | www.lamrc.com |
| n&k | www.nandk.com |
| Nova | www.nova.co.il |
| Rodel | www.rodel.com |
| Strasbaugh | www.strasbaugh.com |
| Verteq | www.verteq.com |
