Packaging Foundry Employs MES to Manage Production

Abpac said it plans to use the MES to integrate its enterprise resource planning (ERP) systems and inventory management system and to link real-time information to the Internet for customer access. Work-in-progress (WIP) tracking is one of the basic functions of an MES. Abpac will use it to produce WIP reports configured and formatted according to customer requirements. Web site accounts and e-mail are among the methods Abpac is preparing to use to make these reports available to customers.

Abpac has previously announced that it is using ESEC's (Cham, Switzerland) Autoline work cells. In many cases, the level of automation provided by systems like Autoline are considered to be sufficient in a back-end operation. When a cassette or magazine of products is loaded into the work cell, it is routed through a number of process steps automatically, wasting little time between steps. Adding an MES on top of that can minimize the time that the work cell waits for material, as well as ensuring that the work cell and its components receive the correct recipes. The MES is expected to provide overall seamless flow integration and data collection, whether individual steps are done in an automated work cell or manually.

Work is currently being done to improve chip traceability. The use of an MES in a packaging and assembly house can be instrumental in meeting the upcoming traceability requirements.

Die-Up BGAs Handle up to 5W

ProLinx Labs (San Jose, CA.) introduced a die-up thermal enhanced ball-grid array (BGA) substrate designed to dissipate up to 5 W. Called the Copper-Core BGA (C2BGA), it uses a copper core to act as a heat slug.

The use of BGA substrates typically requires the use of heat sinks, increased airflow or thermally enhanced cavity-down substrates when power dissipation needs reach 3 or 4 W. For the same size die, the cavity-down substrate would require a larger footprint, since the die-up substrate does not have a cavity. According to the company, the thermal performance of the C2BGA is comparable to that of cavity down BGA packages, dissipating about 13°C/W with no airflow on a 4 W part.

To keep the footprint down, electrical connections are routed through the copper core using what the company calls "micro islands." Using a proprietary process, an annular hole is etched through the copper core, which is then filled with a dielectric material. The result is an insulated via with no drilling or plating tails. The copper via is also solid, rather than deposited or plated, to provide good thermal conduction.

A "micro filled via" process is used to build up routing layers on top of the copper core. The micro filled via process uses a photo-imageable dielectric, so drilling is not required for any of the vias in the substrate.

The company provides PC-based design software, which can produce the necessary CAD files for producing the photomasks, in addition to helping chip designers determine optimum bond pad placement on the die.

The size of the micro island via is defined by lithography and the nature of the etching process. For that reason, routing density can be higher than is possible using drilled vias. The company also believes that the package could theoretically be scaled to the point of being a chip scale package.