SEMATECH Creates a Budget for Process-Induced Defects

The Roadmap estimates process-specific defect densities for 0.25 µm to 0.05 µm devices.

Staff -- Semiconductor International, 1/1/1998

The new SIA Roadmap proposes defect targets for the 0.25 µm and future generations of devices based on 60% yield in a device's first year of production and 85-95% yields for mature products (Table 1). SEMATECH defines process-induced defects (PIDs) per square meter as follows:

where F = faults per mask level
S = minimum defect size
n = technology node

Average PIDs for the 0.25 µm generation were determined using results of a 1996 study of 1997 PIDs at SEMA-TECH member companies. For yield and defect density correlation, SEMATECH used the negative binomial yield model:

where
Y = 60%
A = critical area
a = 2
Do = defect density

The table presents worst case defect budgets assuming that all process levels are at minimum device geometries, even though relaxed geometries exist on all devices within any given process node.

The 1997 Roadmap, focusing on equipment and PIDs, calls for continued development and availability of defect detection, review and classification technologies that can combine greater sensitivity with high throughput. One of the greatest existing challenges is detecting defects associated with high-aspect-ratio contacts and combinations of canals and vias in dual-damascene structures.

SEMATECH identifies the five most difficult defect reduction challenges through the 0.1 µm (100 nm) generation as follows:

• To develop, validate and use accurate defect budget models requiring new test structures; correlation of PIDs, particles per wafer pass, product inspections and in situ measurements; and impact of within-wafer variations on yield predictions;
• To inspect high-aspect-ratio contacts, vias and trenches solving the issue of poor transmission of energy into bottom of via and subsequent detection;
• To correlate trace impurity specifications with device yield by developing test structures and models capable of determining impact of trace metallics, ions and organics on device performance, reliability and yield;
• To isolate faults with increasing device complexity ability to rapidly isolate features on non-arrayed (i.e., non-memory) chips;
• To build defect-free, intelligent equipment using better models (chemistry/contamination), materials technology, software and sensors to provide robust process tools capable of failure prediction and automated correct action response.

PDF version of the table below (6kB)