New Gate Dielectric Material Needed
Two wafer processing challenges are defined in the 1997 Roadmap: the need for a new gate dielectric and, eventually, a new interconnect strategy.
Staff -- Semiconductor International, 1/1/1998
| The 1997 National Technology Roadmap for Semiconductors spells out some important requirements and challenges in the years ahead for assembly and packaging technologies. It says that assembly and packaging needs are driven as much by market application as by silicon technology, and of course, that cost will drive technology trade-offs for all market segments.
According to the new 1997 National Technology Roadmap for Semiconductors (officially released in December), the gate dielectric has emerged as one of the most difficult challenges for future device scaling.
Today, most gate dielectrics are thermally grown oxides (SiO2) and are of very high quality. Continued scaling requires that these oxides be made thinner and thinner now only 40-50 thick in the 0.25 µm (250 nm) generation, they are expected to shrink to 30-40 (180 nm), 20-30 (150 nm), 15-20 (100 nm), <15 (70 nm) and <10 for the 50 nm device generation. The problem is tunneling currents, which could preclude the use of SiO2 dielectric layers below about 15-20 thickness where tunneling currents >1 A/cm2 are predicted. According to the 1997 Roadmap, since tunneling currents will scale exponentially with further thickness reductions, phase-out of this dielectric material is likely beyond the 100 nm node, which is expected to be in production around the year 2006. zmo suitable alternative high-dielectric constant material has been identified with the stability and interface characteristics to serve as a gate dielectric. Years of research and development are required to identify and qualify a suitable alternative material,states the Roadmap Front End Processes technology working group. The near-term gate dielectric solution requires the fabrication and use of ultrathin silicon oxide, oxynitride films or silicon nitride films, according to the Roadmap. The latter film shows attractive boron diffusion penetration resistance and a moderately higher dielectric constant value of 7. Near-term solutions will impose severe restraints on surface preparation, pre- and post-process ambient control, silicon compatible materials development (gate electrodes and contacts, for example) and post processing thermal budgets. Long-term solutions require the identification of materials with a higher dielectric constant (>20 suggested) with other electrical characteristics (e.g., stability and interface state densities) and reliability approaching that of high-quality gate SiO2. The Roadmappers say a major problem with a material other than SiO2 is the probability that a very thin SiO2 layer will still be required at the channel and/or gate electrode to preserve interface state characteristics. This would severely degrade any benefits that accrue from the use of the high-k dielectric. To meet future requirements defined in the Roadmap, a high-k dielectric must have a bandgap of 4-5 eV with a barrier height of >1 eV to limit thermionic emission and Fowler-Nordheim tunneling. In addition, the candidate dielectric material must have negligible trap densities to inhibit Frenkle-Poole tunneling. Finally, the material must have excellent diffusion barrier properties to prevent gate material (or gate dopant) contamination of the transistor channel. Interconnects Beyond 100 nmThe 1997 Roadmap held few surprises in terms of interconnect technology, basically forecasting a long life for aluminum/SiO2 and a greatly expanded role of copper (Cu) and low-k materials at least until the 100 nm technology node. "Currently envisaged potential solutions for 100 nm are to extend the use of Cu metalization," states the Roadmap, "but these material solutions alone are inadequate to meet the stated performance requirements." One potential solution appears to be new design and layout techniques that manage signal delay on a local scale. The use of Cu and lowest possible (k;1) dielectric will provide, at best, a signal delay improvement of 6X. The potential of making further order of magnitude improvements in interconnect capability will be accomplished primarily through design, according to the Roadmap. Interconnect systems that are structured properly (such as neural network implementations) could have much greater computational bandwidth and higher yield because of their inherent robustness to defects. Other solutions include the use of 3-D devices and on-chip/off-chip optical interconnects. Research breakthroughs might allow the use of high-temperature superconductors combined with lower temperature chip operation (Tc near 400K), provided these materials can meet current density requirements. |
|
Company News
|
Applied Materials (Santa Clara, Calif.) announced a number of large equipment orders from Asian companies, including ones from TSMC ($96 million), Hyundai ($35 million), Anam ($52 million) and Chartered ($73 million). Applied Materials announced record results for its fourth quarter, with net sales of $1.28 billion.
